PCM9211
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SBAS495 –JUNE 2010
Register 3Ch–3Dh, PD Buffer (Burst Preamble PD Output Register)
Address: 3Ch, Read-Only
DATA
Reg Name
Default Value
Memo
B7
PD7
N/A
B6
PD6
N/A
B5
PD5
N/A
B4
PD4
N/A
B3
PD3
N/A
B2
PD2
N/A
B1
PD1
N/A
B0
PD0
N/A
Address: 3Dh, Read-Only
DATA
Reg Name
Default Value
Memo
B7
PD15
N/A
B6
PD14
N/A
B5
PD13
N/A
B4
PD12
N/A
B3
B2
PD10
N/A
B1
PD9
N/A
B0
PD8
N/A
PD11
N/A
PD[15:0]: Burst Preamble PD, Length Code (Number of bits)
PD[15:0] is updated at the time when PC[15:0] is updated. PD[15:0] is never updated when only PC[15:0] is
updated. Register 2Ch/OPCRNW0 or Register 2Dh/OPCRNW1 inform the system that PC[15:0] is updated.
Register 40h, System Reset Control
(Address: 40h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
MRST
1
B6
SRST
1
B5
ADDIS
0
B4
RXDIS
0
B3
RSV
0
B2
RSV
0
B1
TXDIS
0
B0
XODIS
0
MRST: Mode Control Register Reset for All Functions
0: Set default value
1: Normal operation (default)
SRST: System Reset for ADC
0: Reset
1: Normal operation (default)
To return the MRST, SRST bit to '0' is not necessary because the MRST, SRST bit is automatically
set to '1'.
ADDIS: Power Down for ADC
0: Normal operation (default)
1: Power down
SCK must be provided to disable ADC by ADDIS = 1.
RXDIS: Power Down for DIR
0: Normal operation (default)
1: Power down
TXDIS: Power Down for DIT
0: Normal operation (default)
1: Power down
XODIS: Power Down for OSC
0: Normal operation (default)
1: Power down
XODIS is superior to OSCAUTO.
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