PCI6x21/PCI6x11
MFUNC1
PIC
IRQ3
IRQ4
IRQ5
IRQ15
IRQ9
IRQ10
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
Figure 3−11. IRQ Implementation
Power-on software is responsible for programming the multifunction routing status register to reflect the IRQ
configuration of a system implementing the PCI6x21/PCI6x11 controller. The multifunction routing status register is
a global register that is shared between the four PCI6x21/PCI6x11 functions. See Section 4.36, Multifunction Routing
Status Register, for details on configuring the multifunction terminals.
The parallel ISA-type IRQ signaling from the MFUNC6−MFUNC0 terminals is compatible with the input signal
requirements of the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs.
Design constraints may demand more MFUNC6−MFUNC0 IRQ terminals than the PCI6x21/PCI6x11 controller
makes available.
3.7.4 Using Parallel PCI Interrupts
Parallel PCI interrupts are available when exclusively in parallel PCI interrupt/parallel ISA IRQ signaling mode, and
when only IRQs are serialized with the IRQSER protocol. The INTA, INTB, INTC, and INTD can be routed to MFUNC
terminals (MFUNC0, MFUNC1, MFUNC2, and MFUNC4). If bit 29 (INTRTIE) is set in the system control register (PCI
offset 80h, see Section 4.29), then INTA and INTB are tied internally. When the TIEALL bit is set, all four functions
return a value of 01h on reads from the interrupt pin register for both parallel and serial PCI interrupts.
The INTRTIE and TIEALL bits affect the read-only value provided through accesses to the interrupt pin register (PCI
offset 3Dh, see Section 4.24). Table 3−11 summarizes the interrupt signaling modes.
Table 3−11. Interrupt Pin Register Cross Reference
INTPIN
Function 0
(CardBus)
INTPIN
Function 1
(CardBus)
INTPIN
Function 3
(Flash Media)
INTPIN
Function 4
(SD Host)
INTPIN
Function 5
(Smart Card)
INTRTIE TIEALL
Bit
Bit
Determined by bits 6−5
(INT_SEL field) in flash
media general control
Determined by bits 6−5
(INT_SEL field) in SD host
general control register
(see Section 8.22)
Determined by bits 6−5
(INT_SEL field) in Smart
Card general control
0
0
0x01 (INTA) 0x02 (INTB)
1
0
1
0x01 (INTA) 0x01 (INTA)
0x01 (INTA) 0x01 (INTA)
register (see Section 7.21)
register (see Section 9.22)
X
0x01 (INTA)
0x01 (INTA)
0x01 (INTA)
3.7.5 Using Serialized IRQSER Interrupts
The serialized interrupt protocol implemented in the PCI6x21/PCI6x11 controller uses a single terminal to
communicate all interrupt status information to the host controller. The protocol defines a serial packet consisting of
a start cycle, multiple interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI
clock. The packet data describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA, INTB, INTC, and
INTD. For details on the IRQSER protocol, refer to the document Serialized IRQ Support for PCI Systems.
3.7.6 SMI Support in the PCI6x21/PCI6x11 Controller
The PCI6x21/PCI6x11 controller provides a mechanism for interrupting the system when power changes have been
made to the PC Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance
interrupt (SMI) scheme. SMI interrupts are generated by the PCI6x21/PCI6x11 controller, when enabled, after a write
cycle to either the socket control register (CB offset 10h, see Section 6.5) of the CardBus register set, or the ExCA
power control register (ExCA offset 02h/42h/802h, see Section 5.3) causes a power cycle change sequence to be
sent on the power switch interface.
3−18
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