Table 2−5. PC Card Power Switch Terminals
Internal pullup/pulldown resistors, power rail designation, and pin strapping are not applicable for the power switch
terminals.
TERMINAL
I/O
TYPE
EXTERNAL
COMPONENTS
DESCRIPTION
INPUT OUTPUT
NAME
NO.
Power switch clock. Information on the DATA line is sampled at the rising edge of
CLOCK. CLOCK defaults to an input, but can be changed to an output by using bit 27
(P2CCLK) in the system control register (offset 80h, see Section 4.29).
PCMCIA power
switch
CLOCK
L06
I/O
TTLI1
TTLO1
Power switch data. DATA is used to communicate socket power control information
serially to the power switch.
PCMCIA power
switch
DATA
N01
N02
O
O
LVCO1
LVCO1
Power switch latch. LATCH is asserted by the controller to indicate to the power
switch that the data on the DATA line is valid.
PCMCIA power
switch
LATCH
Table 2−6. PCI System Terminals
Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI terminals.
TERMINAL
I/O
TYPE
POWER
RAIL
EXTERNAL
COMPONENTS
DESCRIPTION
INPUT
NAME NO.
Global reset. When the global reset is asserted, the GRST signal causes the
controller to place all output buffers in a high-impedance state and reset all internal
registers. When GRST is asserted, the controller is completely in its default state. For
systems that require wake-up from D3, GRST is normally asserted only during initial
boot. PRST must be asserted following initial boot so that PME context is retained
when transitioning from D3 to D0. For systems that do not require wake-up from D3,
GRST must be tied to PRST. When the SUSPEND mode is enabled, the controller is
protected from the GRST, and the internal registers are preserved. All outputs are
placed in a high-impedance state, but the contents of the registers are preserved.
Power-on reset or
tied to PRST
GRST
T01
I
LVCI2
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI
signals are sampled at the rising edge of PCLK.
PCLK
PRST
P05
R03
I
I
PCII3
PCII3
V
CCP
PCI bus reset. When the PCI bus reset is asserted, PRST causes the controller to
place all output buffers in a high-impedance state and reset some internal registers.
When PRST is asserted, the controller is completely nonfunctional. After PRST is
deasserted, the controller is in a default state.
V
CCP
When SUSPEND and PRST are asserted, the controller is protected from PRST
clearing the internal registers. All outputs are placed in a high-impedance state, but
the contents of the registers are preserved.
2−15
TI [ TEXAS INSTRUMENTS ]
