Table 2−4. Power Supply Terminals
Output description, internal pullup/pulldown resistors, and the power rail designation are not applicable for the power
supply terminals.
TERMINAL
NAME NUMBER
I/O
TYPE
EXTERNAL
COMPONENTS
PIN STRAPPING
(IF UNUSED)
DESCRIPTION
INPUT
N12, U14,
U16
AGND
Analog circuit ground terminals
GND
GND
NA
NA
Analog circuit power terminals. A parallel combination of high
frequency decoupling capacitors near each terminal is suggested,
such as 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering
capacitors are also recommended. These supply terminals are
separated from VDPLL_33 internal to the controller to provide
noise isolation. They must be tied to a low-impedance point on the
circuit board.
0.1-µF, 0.001-µF,
and 10-µF
capacitors tied to
R13, R14,
V17
AVDD
AGND
G07, G08,
G13, H13,
J09, J10,
J11, K09,
K10, K11,
L08, L09,
L10, L11,
L12, M08
GND
Digital ground terminal
GND
NA
H08, H09,
H10, H11,
H12, J08,
J12, K08,
K12, M07,
M09, M10,
M12, N07
V
V
Power supply terminal for I/O and internal voltage regulator
PWR
PWR
NA
CC
Clamp voltage for PC Card A interface. Matches card A signaling
environment, 5 V or 3.3 V
A05, A11
Float
CCA
Clamp voltage for PC Card B interface. Matches card B signaling
environment, 5 V or 3.3 V
V
V
D19, K19
PWR
PWR
Float
NA
CCB
W03, W10
Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V
CCP
1.5-V PLL circuit power terminal. An external capacitor (0.1 µF
recommended) must be placed between terminals T18 and T17
(VSSPLL) when the internal voltage regulator is enabled
(VR_EN = 0 V). When the internal voltage regulator is disabled,
1.5-V must be supplied to this terminal and a parallel combination
of high frequency decoupling capacitors near the terminal is
suggested, such as 0.1 µF and 0.001 µF. Lower frequency 10-µF
filtering capacitors are also recommended.
0.1-µF, 0.001-µF,
and 10-µF
capacitors tied to
VDPLL_15
T18
NA
VSPLL
3.3-V PLL circuit power terminal. A parallel combination of high
frequency decoupling capacitors near the terminal is suggested,
such as 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering
capacitors are also recommended. This supply terminal is
separated from AVDD internal to the controller to provide noise
isolation. It must be tied to a low-impedance point on the circuit
board. When the internal voltage regulator is disabled
(VR_EN = 3.3 V), no voltage is required to be supplied to this
terminal.
0.1-µF, 0.001-µF,
and 10-µF
capacitors tied to
VDPLL_33
V19
PWR
NA
VSPLL
Pulled directly to
GND
VR_EN
H02
Internal voltage regulator enable. Active low
1.5-V output from the internal voltage regulator
FT
FT
NA
NA
0.1-µF capacitor
tied to GND
VR_PORT
H01, M19
PWR
PLL circuit ground terminal. This terminal must be tied to the
low-impedance circuit board ground plane.
VSSPLL
P14, T17
GND
NA
2−14
TI [ TEXAS INSTRUMENTS ]
