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SCPS131E – AUGUST 2005 – REVISED MAY 2008
SIMPLIFIED SCHEMATIC OF P-PORT I/Os
Data From
Shift Register
Configuration
Register
Data From
Shift Register
Write Configuration
Pulse
Write Pulse
D
FF
CLK Q
Q
100 kW
D
FF
CLK Q
Output Port
Register
Q
Output Port
Register Data
Q1
V
CC
I/O Pin
Q2
Input Port
Register
D
FF
Read Pulse
CLK Q
Q
GND
Input Port
Register Data
To INT
Data From
Shift Register
D
FF
Q
Polarity
Register Data
Write Polarity
Pulse
CLK Q
Polarity Inversion
Register
(1)
At power-on reset, all registers return to default values.
I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input
voltage may be raised above V
CC
to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In
this case, there are low-impedance paths between the I/O pin and either V
CC
or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
Copyright © 2005–2008, Texas Instruments Incorporated
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