PCA9555
REMOTE 16-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
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SCPS131D–AUGUST 2005–REVISED OCTOBER 2006
Reads
The bus master first must send the PCA9555 address with the least-significant bit set to a logic 0 (see Figure 4
for device address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again, but this time, the least-significant bit is set to a logic 1. Data
from the register defined by the command byte then is sent by the PCA9555 (see Figure 8 through Figure 10).
After a restart, the value of the register defined by the command byte matches the register being accessed when
the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart
occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The
original command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into
the register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read,
but the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read, the
next byte read is Input Port 0.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
Data From Lower
or Upper Byte
Slave Address
Slave Address
of Register
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Master
Data
Command Byte
S
0
1
0
0
A2 A1 A0
0
A
A
S
0
1
0
0
A2 A1 A0
1
A
MSB
LSB A
First Byte
R/W
R/W
At this moment, master transmitter
becomes master receiver, and
slave-receiver becomes
slave-transmitter.
Data From Upper
or Lower Byte
of Register
No Acknowledge
From Master
MSB
LSB NA
P
Data
Last Byte
Figure 8. Read From Register
1
2
3
4
5
6
7
8
9
SCL
SDA
I0.x
I1.x
I0.x
I1.x
3
S
0
1
0
0
A2 A1 A0
1
A
7
6
5
4
3
2
1
0
A
7
6
5
4
3
2
1
0
A
7
6
5
4
3
2
1
0
A
7
6
5
4
2
1
0
1
P
Acknowledge
From Slave
Acknowledge
From Master
Acknowledge
From Master
Acknowledge
From Master
R/W
No Acknowledge
From Master
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
INT
t
iv
t
ir
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 8 for these details).
Figure 9. Read Input Port Register, Scenario 1
11
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