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REMOTE 16-BIT I C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
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SCPS130D – AUGUST 2005 – REVISED MARCH 2007
SIMPLIFIED SCHEMATIC OF P-PORT I/Os
Data From
Shift Register
Configuration
Register
Data From
Shift Register
Write Configuration
Pulse
Write Pulse
D
FF
CLK Q
Q
D
FF
CLK Q
Output Port
Register
Q
Output Port
Register Data
V
CC
Q1
I/O Pin
Q2
Input Port
Register
D
FF
Read Pulse
CLK Q
Q
GND
Input Port
Register Data
To INT
Data From
Shift Register
D
FF
Q
Polarity
Register Data
Write Polarity
Pulse
CLK Q
Polarity Inversion
Register
(1)
At power-on reset, all registers return to default values.
I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The
input voltage may be raised above V
CC
to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In
this case, there are low-impedance paths between the I/O pin and either V
CC
or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
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