BOARD LAYOUT
+5V
VCC
Achieving optimum performance with a high-frequency am-
plifier such as the OPA846 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that optimize performance include:
Power-supply decoupling
not shown.
VO
OPA846
0.1µF
48Ω
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability: on the
noninverting input, it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted ca-
pacitance, create a window around the signal I/O pins leave
opened in all of the ground and power planes around those
pins.
VEE
–5V
+5V
RG
50Ω
RF
1kΩ
VI
5kΩ
5kΩ
±200mV Output Adjustment
20kΩ
b) Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At
the device pins, the ground and power plane layout should
not be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections should always be decoupled with these capaci-
tors. Larger (2.2µF to 6.8µF) decoupling capacitors are
effective at lower frequencies, and are recommended on the
main supply pins. These may be placed somewhat further
from the device and shared among several devices in the
same area of the PC board.
100Ω
0.1µF
V
RF
O = –
VI
= –20V/V
RG
–5V
FIGURE 16. DC-Coupled, Inverting Gain of –20V/V with
Output Offset Adjustment.
THERMAL ANALYSIS
The OPA846 does not require heat sinking or airflow in most
applications. Maximum desired junction temperature sets the
maximum allowed internal power dissipation as described
following. In no case should the maximum junction tempera-
ture be allowed to exceed +150°C.
c) Careful selection and placement of external compo-
nents preserves the high-frequency performance of the
OPA846. Use resistors that have low reactance at high
frequencies. Surface-mount resistors work best and allow a
tighter overall layout. Metal-film and carbon composition,
axially leaded resistors can also provide good high-fre-
quency performance. Again, keep their leads and PC board
trace length as short as possible. Never use wire wound type
resistors in a high-frequency application. Since the output pin
and inverting input pin are the most sensitive to parasitic
capacitance, always position the feedback and series output
resistor, if any, as close as possible to the output pin. Other
network components, such as noninverting input termination
resistors, should also be placed close to the package. Where
double-feedback side component mounting is allowed, place
the feedback resistor directly under the package on the other
side of the board between the output and inverting input pins.
Even with a low parasitic capacitance shunting the external
resistors, excessively high resistor values can create signifi-
cant time constants that can degrade performance. Good
axial metal-film or surface-mount resistors have approxi-
mately 0.2pF in shunt with the resistor. For resistor values
> 1.5kΩ, this parasitic capacitance can add a pole and/or a
zero below 500MHz that can effect circuit operation. Keep
resistor values as low as possible consistent with load driving
considerations. It has been suggested here that a good
starting point for design would be set the RG be set to 50Ω.
Doing this automatically keeps the resistor noise terms low,
and minimizes the effect of parasitic capacitance. Transim-
pedance applications can use much higher resistor values.
The compensation techniques described in this data sheet
allow excellent frequency response control, even with very
high feedback resistor values.
Operating junction temperature (TJ) is given by TA + PD • θJA.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and additional power dissipated in the
output stage (PDL) to deliver load power. Quiescent power is
the specified no-load supply current times the total supply
voltage across the part. PDL depends on the required output
signal and load but would, for a grounded resistive load, be
at a maximum when the output is fixed at a voltage equal to
1/2 either supply voltage (for equal bipolar supplies). Under
2
this worst-case condition, PDL = VS /(4 • RL), where RL
includes the feedback network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using an
OPA846IDBV (SOT23-5 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85°C and driving a grounded 100Ω load at +2.5VDC
.
PD = 10V(13.9mA) + 52/(4 • (100Ω || 500Ω)) = 214mW
Maximum TJ = +85°C + (0.21W • 150°C/W) = 117°C
All actual applications will operate at a lower junction tem-
perature than the 117°C computed above. Compute the
actual stage power to get an accurate estimate of maximum
junction temperature, or use the results shown here as an
absolute maximum.
OPA846
18
SBOS250C
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