difference between the two equal test-tone power levels
and these intermodulation spurious power levels is given by
∆dBc = 2 • (IM3 – PO) where IM3 is the intercept taken from
the typical characteristic curve and PO is the power level in
dBm at the 50Ω load for one of the two closely-spaced test
frequencies. At 5MHz for instance, the OPA846 at a gain of
+10V/V has an intercept of 48dBm at a matched 50Ω load.
800
700
600
500
400
300
200
100
0
Mean = –0.01
Standard Deviation = 0.08
Total Count = 2952
If the full envelope of the two frequencies needs to be 2VPP
,
this requires each tone to be 4dBm. The 3rd-order
intermodulation spurious tones are 2 • (48 – 4) = 88dBc
below the test-tone power level (–84dBm). If this same 2VPP
,
2-tone envelope were delivered directly into the input of an
A/D converter—without the matching loss or the loading of
the 50Ω network—the intercept would increase to at least
54dBm. With the same signal and gain conditions, but now
driving directly into a light load, the spurious tones will then
be at least 2 • (54 – 4) = 100dBc below the 4dBm test-tone
power levels centered on 5MHz.
µA
FIGURE 15. Input Offset Current Distribution.
For example, one way to add bias current cancellation to the
circuit of Figure 1 would be to insert a 20Ω series resistor into
the noninverting input from the 50Ω terminating resistor. When
the 50Ω source resistor is DC-coupled, this increases the
source resistances for the noninverting input bias current to
45Ω. Since this is now equal to the resistance looking out of
the inverting input (RF || RG), the circuit cancels the gains for
the bias currents to the output, leaving only the offset current
times the feedback resistor as a residual DC error term at the
output. Using the 453Ω feedback resistor, this output error is
now less than ±600nA • 453Ω = ±272µV over the full tempera-
ture range.
DC ACCURACY AND OFFSET CONTROL
The OPA846 can provide excellent DC signal accuracy due
to its high open-loop gain, high common-mode rejection, high
power-supply rejection, and low input offset voltage and bias
current offset errors. To take full advantage of its low ±0.6mV
maximum (25°C) input offset voltage, careful attention to
input bias current cancellation is also required. The low-noise
input stage for the OPA846 has a relatively high input bias
current (10µA typical into the pins), but with a very close
match between the two input currents—typically ±100nA
input offset current. Figures 14 and 15 show typical distribu-
tions of input offset voltage and current for the OPA846. The
total output offset voltage can be considerably reduced by
matching the source impedances looking out of the two pins.
A fine-scale output offset null, or DC operating point adjust-
ment, is often required. Numerous techniques are available
for introducing a DC offset control into an op amp circuit.
Most of these techniques eventually reduce to setting up a
DC current through the feedback resistor. One key consider-
ation to selecting a technique is to ensure that it has minimal
impact on the desired signal path frequency response. If the
signal path is intended to be noninverting, the offset control
is best applied as an inverting summing signal to avoid
interaction with the signal source. If the signal path uses the
inverting mode, applying an offset control to the noninverting
input can be considered. For a DC-coupled inverting input
signal, this DC offset signal sets up a DC current back into
the source that must be considered. An offset adjustment
placed on the inverting op amp input can also change the
noise gain and frequency response flatness. See Figure 16
for one example of an offset adjustment for a DC-coupled
signal path that has minimum impact on the signal frequency
response. In this case, the input is brought into an inverting
gain resistor with the DC adjustment as an additional current
summed into the inverting node. The resistor values for
setting this offset adjustment are chosen to be much larger
than the signal path resistors. This ensures that the adjust-
ment has minimal impact on the loop gain and hence, the
frequency response.
600
Mean = –0.01
Standard Deviation = 0.17
Total Count = 2952
500
400
300
200
100
0
mV
FIGURE 14. Input Offset Voltage Distribution.
OPA846
SBOS250C
17
www.ti.com
TI [ TEXAS INSTRUMENTS ]
