OMAP-L137 Low-Power Applications Processor
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
CTRPHS
(phase register−32 bit)
APWM mode
SYNCIn
CTR_OVF
OVF
CTR [0−31]
PWM
TSCTR
(counter−32 bit)
SYNCOut
Delta−mode
PRD [0−31]
compare
logic
RST
CMP [0−31]
32
CTR=PRD
CTR [0−31]
PRD [0−31]
CTR=CMP
32
eCAPx
32
32
LD1
CAP1
(APRD active)
Polarity
select
LD
APRD
shadow
32
CMP [0−31]
32
LD2
CAP2
(ACMP active)
Polarity
select
LD
Event
qualifier
Event
Pre-scale
32
ACMP
shadow
Polarity
select
32
32
LD3
LD4
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
Polarity
select
LD
4
Capture events
4
CEVT[1:4]
Interrupt
Trigger
and
Flag
Continuous /
Oneshot
Capture Control
to PIE
CTR_OVF
CTR=PRD
CTR=CMP
control
Figure 6-41. eCAP Functional Block Diagram
Table 6-65 is the list of the ECAP registers.
Table 6-65. ECAPx Configuration Registers
ECAP0
BYTE ADDRESS
ECAP1
BYTE ADDRESS
ECAP2
REGISTER NAME
DESCRIPTION
BYTE ADDRESS
0x01F0 8000
0x01F0 8004
0x01F0 8008
0x01F0 6000
0x01F0 6004
0x01F0 6008
0x01F0 7000
0x01F0 7004
0x01F0 7008
TSCTR
CTRPHS
CAP1
Time-Stamp Counter
Counter Phase Offset Value Register
Capture 1 Register
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