ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢄ ꢆ ꢈ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢃ ꢆ ꢈ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢃ ꢆꢇ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS272F − JULY 2000 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.0 to P2.2, P2.6, and P2.7 input/output with Schmitt-trigger
P2SEL.x
0
0: Input
P2DIR.x
Direction Control
From Module
1: Output
1
0
1
P2OUT.x
Module X OUT
P2.0/ACLK
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.6/ADC12CLK
P2.7/TA0
Pad Logic
P2IN.x
EN
D
Bus Keeper
Module X IN
P2IRQ.x
CAPD.X
P2IE.x
P2IFG.x
EN
Interrupt
Edge
Select
Q
Set
Interrupt
Flag
P2IES.x
P2SEL.x
x: Bit Identifier 0 to 2, 6, and 7 for Port P2
Dir. CONTROL
PnSel.x
PnDIR.x
PnOUT.x MODULE X OUT PnIN.x
MODULE X IN
PnIE.x PnIFG.x PnIES.x
FROM MODULE
P2Sel.0
P2Sel.1
P2Sel.2
P2Sel.6
P2Sel.7
P2DIR.0
P2DIR.1
P2DIR.2
P2DIR.6
P2DIR.7
P2DIR.0
P2OUT.0
P2OUT.1
P2OUT.2
P2OUT.6
P2OUT.7
ACLK
DV
P2IN.0
P2IN.1
P2IN.2
P2IN.6
P2IN.7
unused
P2IE.0 P2IFG.0 P2IES.0
P2IE.1 P2IFG.1 P2IES.1
P2IE.2 P2IFG.2 P2IES.2
P2IE.6 P2IFG.6 P2IES.6
P2IE.7 P2IFG.7 P2IES.7
‡
P2DIR.1
INCLK
CCI0B
SS
†
‡
P2DIR.2
CAOUT
¶
P2DIR.6
ADC12CLK
unused
unused
§
Out0 signal
P2DIR.7
†
‡
§
¶
Signal from Comparator_A
Signal to Timer_A
Signal from Timer_A
ADC12CLK signal is output of the 12-bit ADC module
41
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