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SLAS272F − JULY 2000 − REVISED JUNE 2004
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External Reset
Watchdog
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
15, highest
Flash memory
NMI
Oscillator Fault
Flash memory access violation
NMIIFG (see Notes 1 & 4)
OFIFG (see Notes 1 & 4)
ACCVIFG (see Notes 1 & 4)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
14
Timer_B7 (see Note 5)
TBCCR0 CCIFG (see Note 2)
Maskable
0FFFAh
0FFF8h
13
12
TBCCR1 to 6 CCIFGs,
TBIFG (see Notes 1 & 2)
Timer_B7 (see Note 5)
Maskable
Comparator_A
Watchdog timer
USART0 receive
USART0 transmit
ADC12 (see Note 6)
Timer_A3
CAIFG
WDTIFG
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
11
10
9
URXIFG0
UTXIFG0
8
ADC12IFG (see Notes 1 & 2)
TACCR0 CCIFG (see Note 2)
7
6
TACCR1 CCIFG,
TACCR2 CCIFG,
Timer_A3
Maskable
0FFEAh
5
TAIFG (see Notes 1 & 2)
P1IFG.0 to P1IFG.7
(see Notes 1 & 2)
I/O port P1 (eight flags)
Maskable
Maskable
0FFE8h
4
USART1 receive
USART1 transmit
URXIFG1
UTXIFG1
0FFE6h
0FFE4h
3
2
P2IFG.0 to P2IFG.7
(see Notes 1 & 2)
I/O port P2 (eight flags)
Maskable
0FFE2h
0FFE0h
1
0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
4. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable
it.
5. Timer_B7 in MSP430x14x(1) family has 7 CCRs; Timer_B3 in MSP430x13x family has 3 CCRs. In Timer_B3 there are only interrupt
flags TBCCR0, 1, and 2 CCIFGs and the interrupt-enable bits TBCCTL0, 1, and 2 CCIEs.
6. ADC12 is not implemented on the 14x1 devices.
13
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