MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340G − MAY 2001 − REVISED JUNE 2004
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
Address
0h
7
6
5
ACCVIE
rw-0
Address
1h
7
BTIE
rw-0
6
5
4
NMIIE
rw-0
4
3
2
3
2
1
OFIE
rw-0
1
0
WDTIE
rw-0
0
WDTIE:
OFIE:
NMIIE:
ACCVIE:
BTIE:
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is config-
ured in interval timer mode.
Oscillator-fault-interrupt enable
Nonmaskable-interrupt enable
Flash access violation interrupt enable
Basic Timer1 interrupt enable
interrupt flag register 1 and 2
Address
02h
7
6
5
4
NMIIFG
rw-0
Address
3h
7
BTIFG
rw-0
6
5
4
3
2
3
2
1
OFIFG
rw-1
1
0
WDTIFG
rw-(0)
0
WDTIFG:
OFIFG:
NMIIFG:
BTIFG:
Set on watchdog-timer overflow (in watchdog mode) or security key violation. Reset with V
CC
power-up,
or a reset condition at the RST/NMI pin in reset mode.
Flag set on oscillator fault
Set via RST/NMI pin
Basic Timer1 interrupt flag
module enable registers 1 and 2
Address
04h/05h
Legend: rw:
rw-0:
Bit Can Be Read and Written
Bit Can Be Read and Written. It Is Reset by PUC.
SFR Bit Not Present in Device
7
6
5
4
3
2
1
0
12
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