MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340G − MAY 2001 − REVISED JUNE 2004
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the ROM with an address range
0FFFFh − 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
INTERRUPT SOURCE
Power-up
External Reset
Watchdog
Flash memory
NMI
Oscillator Fault
Flash memory access violation
Timer1_A5 (see Note 4)
Timer1_A5 (see Note 4)
Comparator_A
Watchdog Timer
INTERRUPT FLAG
WDTIFG
KEYV
(see Note 1)
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
TA1CCR0 CCIFG (see Note 2)
TA1CCR1 to TA1CCR4
CCIFGs and TA1CTL TAIFG
(see Notes 1 and 2)
CMPAIFG
WDTIFG
SYSTEM INTERRUPT
Reset
WORD ADDRESS
0FFFEh
PRIORITY
15, highest
(Non)maskable
(Non)maskable
(Non)maskable
Maskable
Maskable
Maskable
Maskable
0FFFCh
0FFFAh
0FFF8h
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
14
13
12
11
10
9
8
7
6
Timer_A3/Timer0_A3
TACCR0/TA0CCR0 CCIFG
(see Note 2)
TACCR1/TA0CCR1 and
TACCR2/TA0CCR2 CCIFGs,
and TACLT/TA0CTL TAIFG
(see Notes 1 and 2)
P1IFG.0 to P1IFG.7
(see Notes 1 and 2)
Maskable
0FFECh
Timer_A3/Timer0_A3
Maskable
0FFEAh
5
I/O port P1 (eight flags)
Maskable
0FFE8h
0FFE6h
0FFE4h
4
3
2
1
0, lowest
I/O port P2 (eight flags)
Basic Timer1
NOTES: 1.
2.
3.
4.
P2IFG.0 to P2IFG.7
(see Notes 1 and 2)
BTIFG
Maskable
Maskable
0FFE2h
0FFE0h
Multiple source flags
Interrupt flags are located in the module.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.
Implemented in MSP430x415 and MSP430x417 devices only.
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