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MSP430F6723IPZR 参数 Datasheet PDF下载

MSP430F6723IPZR图片预览
型号: MSP430F6723IPZR
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号微控制器 [MIXED SIGNAL MICROCONTROLLER]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 121 页 / 1013 K
品牌: TI [ TEXAS INSTRUMENTS ]
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MSP430F673x  
MSP430F672x  
www.ti.com  
SLAS731A DECEMBER 2011REVISED APRIL 2012  
Table 5. Terminal Functions, MSP430F67xxIPZ  
TERMINAL  
NAME  
NO. I/O(1)  
PZ  
DESCRIPTION  
SD24_B positive analog input for converter 0(2)  
SD24_B negative analog input for converter 0(2)  
SD24_B positive analog input for converter 1(2)  
SD24_B negative analog input for converter 1(2)  
SD0P0  
SD0N0  
SD1P0  
SD1N0  
1
2
3
4
I
I
I
I
SD24_B positive analog input for converter 2(2) (not available on F672x devices)  
SD2P0  
SD2N0  
5
6
I
SD24_B negative analog input for converter 2(2) (not available on F672x devices)  
SD24_B external reference voltage  
I
I
VREF  
AVSS  
AVCC  
7
8
9
Analog ground supply  
Analog power supply  
Analog power supply selected between AVCC, AUXVCC1, AUXVCC2. Connect  
recommended capacitor value of CVSYS (see Auxiliary Supplies - Recommended  
Operating Conditions).  
VASYS  
10  
General-purpose digital I/O  
Analog input A5 - 10-bit ADC  
P9.1/A5  
P9.2/A4  
P9.3/A3  
11  
12  
13  
I/O  
I/O  
I/O  
General-purpose digital I/O  
Analog input A4 - 10-bit ADC  
General-purpose digital I/O  
Analog input A3 - 10-bit ADC  
General-purpose digital I/O with port interrupt and mappable secondary function  
Default mapping: Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output  
P1.0/PM_TA0.0/VeREF-/A2  
P1.1/PM_TA0.1/VeREF+/A1  
14  
15  
I/O  
I/O  
Negative terminal for the ADC's reference voltage for an external applied reference  
voltage  
Analog input A2 - 10-bit ADC  
General-purpose digital I/O with port interrupt and mappable secondary function  
Default mapping: Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output  
Positive terminal for the ADC's reference voltage for an external applied reference  
voltage  
Analog input A1 - 10-bit ADC  
General-purpose digital I/O with port interrupt and mappable secondary function  
Default mapping: eUSCI_A0 UART receive data; eUSCI_A0 SPI slave out/master in  
Analog input A0 - 10-bit ADC  
P1.2/PM_UCA0RXD/  
PM_UCA0SOMI/A0  
16  
17  
I/O  
I/O  
General-purpose digital I/O with port interrupt and mappable secondary function  
Default mapping: eUSCI_A0 UART transmit data; eUSCI_A0 SPI slave in/master out  
Input/output port of lowest analog LCD voltage (V5)  
P1.3/PM_UCA0TXD/  
PM_UCA0SIMO/R03  
AUXVCC2  
AUXVCC1  
18  
19  
Auxiliary power supply AUXVCC2  
Auxiliary power supply AUXVCC1  
Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect  
recommended capacitor value of CVSYS (see Auxiliary Supplies - Recommended  
Operating Conditions).  
VDSYS(3)  
20  
DVCC  
DVSS  
VCORE(4)  
XIN  
21  
22  
23  
24  
Digital power supply  
Digital ground supply  
Regulated core power supply (internal use only, no external current loading)  
Input terminal for crystal oscillator  
I
(1) I = input, O = output  
(2) It is recommended to short unused analog input pairs and connect them to analog ground.  
(3) The pins VDSYS and DVSYS must be connected externally on board for proper device operation.  
(4) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended  
capacitor value, CVCORE  
.
Copyright © 2011–2012, Texas Instruments Incorporated  
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