MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
Pin Designation, MSP430F673xIPZ
PJ.2/ADC10CLK/TMS
PJ.1/MCLK/TDI/TCLK
RST/NMI/SBWTDIO
PJ.0/SMCLK/TDO
PJ.3/ACLK/TCK
TEST/SBWTCK
P7.1/S10
P6.7/S12
P6.6/S13
P6.5/S14
P6.4/S15
P6.3/S16
P6.2/S17
SD0P0
SD0N0
SD1P0
SD1N0
SD2P0
SD2N0
VREF
AVSS
AVCC
VASYS
P9.1/A5
P9.2/A4
P9.3/A3
P1.0/PM_TA0.0/VeREF-/A2
P1.1/PM_TA0.1/VeREF+/A1
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0
P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03
AUXVCC2
AUXVCC1
VDSYS
DVCC
DVSS
VCORE
XIN
XOUT
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PZ PACKAGE
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
P6.1/S18
P7.0/S11
P8.3/S0
P8.2/S1
P8.1/S2
P8.0/S3
P7.7/S4
P7.6/S5
P7.5/S6
P7.4/S7
P7.3/S8
P7.2/S9
DVSS
DVSYS
P6.0/S19
P5.7/S20
P5.6/S21
P5.5/S22
P5.4/S23
P5.3/S24
P5.2/S25
P5.1/S26
P5.0/S27
P4.7/S28
P4.6/S29
P4.5/S30
P4.4/S31
P4.3/S32
P4.2/S33
P4.1/S34
P4.0/S35
P3.7/PM_SD2DIO/S36
P3.6/PM_SD1DIO/S37
P3.5/PM_SD0DIO/S38
P3.4/PM_SDCLK/S39
P3.3/PM_TA0.2
P3.2/PM_TACLK/PM_RTCCLK
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P3.0/PM_TA2.0/BSL_TX
P2.6/PM_TA1.0
P9.0/TACLK/RTCCLK
P2.7/PM_TA1.1
P8.4/TA1.0
P8.5/TA1.1
P8.6/TA2.0
P8.7/TA2.1
COM0
COM1
COM2
COM3
P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7
P2.3/PM_UCA2TXD/PM_UCA2SIMO
P1.6/PM_UCA0CLK/COM4
P1.7/PM_UCB0CLK/COM5
P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23
P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6
P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13
P2.2/PM_UCA2RXD/PM_UCA2SOMI
P3.1/PM_TA2.1/BSL_RX
AUXVCC3
P2.4/PM_UCA1CLK
P2.5/PM_UCA2CLK
LCDCAP/R33
NOTE: The secondary digital functions on Ports P1, P2, and P3 are fully mappable. The pin designation shows the default
mapping. See
for details.
NOTE: The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
CAUTION: The LCDCAP/R33 pin must be connected to DVSS if not used.
Copyright © 2011–2012, Texas Instruments Incorporated
5
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