MSP430F673x
MSP430F672x
SLAS731A – DECEMBER 2011 – REVISED APRIL 2012
DESCRIPTION
The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with extensive low-
power modes, is optimized to achieve extended battery life in portable measurement applications. The device
features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in 3 µs
(typical).
The MSP430F67xx series are microcontroller configurations with three high-performance 24-bit sigma-delta A/D
converters, a 10-bit analog-to-digital (A/D) converter, four enhanced universal serial communication interfaces
(three eUSCI_A and one eUSCI_B), four 16-bit timers, hardware multiplier, DMA, real-time clock module with
alarm capabilities, LCD driver with integrated contrast control, auxiliary supply system, and up to 72 I/O pins in
100-pin devices and 52 I/O pins in 80-pin devices.
Typical applications for these devices are 2-wire and 3-wire single-phase metering, including tamper-resistant
meter implementations.
Family members available are summarized in
Table 1. Family Members
eUSCI
Device
Flash
(KB)
128
128
96
64
32
16
128
128
96
64
32
16
128
128
96
64
32
16
128
128
96
64
32
16
SRAM
(KB)
8
4
4
4
2
1
8
4
4
4
2
1
8
4
4
4
2
1
8
4
4
4
2
1
SD24_B
Converters
3
3
3
3
3
3
2
2
2
2
2
2
3
3
3
3
3
3
2
2
2
2
2
2
ADC10_A
Channels
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
6 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
3 ext, 2 int
Timer_A
(1)
Channel A:
UART, IrDA,
SPI
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Channel B:
SPI, I
2
C
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I/O
Package
Type
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
100 PZ
80 PN
80 PN
80 PN
80 PN
80 PN
80 PN
80 PN
80 PN
80 PN
80 PN
80 PN
80 PN
MSP430F6736IPZ
MSP430F6735IPZ
MSP430F6734IPZ
MSP430F6733IPZ
MSP430F6731IPZ
MSP430F6730IPZ
MSP430F6726IPZ
MSP430F6725IPZ
MSP430F6724IPZ
MSP430F6723IPZ
MSP430F6721IPZ
MSP430F6720IPZ
MSP430F6736IPN
MSP430F6735IPN
MSP430F6734IPN
MSP430F6733IPN
MSP430F6731IPN
MSP430F6730IPN
MSP430F6726IPN
MSP430F6725IPN
MSP430F6724IPN
MSP430F6723IPN
MSP430F6721IPN
MSP430F6720IPN
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
3, 2, 2, 2
72
72
72
72
72
72
72
72
72
72
72
72
52
52
52
52
52
52
52
52
52
52
52
52
(1)
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
2
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