MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
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12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
For specified performance of ADC12 linearity
parameters using an external reference voltage or
AVCC as reference(1)
0.45
4.8
5.0
fADC12CLK
ADC conversion clock
For specified performance of ADC12 linearity
parameters using the internal reference(2)
2.2 V, 3 V
MHz
4.0
0.45
0.45
4.2
2.4
2.4
4.8
For specified performance of ADC12 linearity
parameters using the internal reference(3)
2.7
Internal ADC12
oscillator(4)
fADC12OSC
tCONVERT
tSample
ADC12DIV = 0, fADC12CLK = fADC12OSC
2.2 V, 3 V
2.2 V, 3 V
5.4 MHz
REFON = 0, Internal oscillator,
ADC12OSC used for ADC conversion clock
2.4
3.1
µs
Conversion time
External fADC12CLK from ACLK, MCLK or SMCLK,
ADC12SSEL ≠ 0
(5)
RS = 400 Ω, RI = 200 Ω, CI = 20 pF,
τ = [RS + RI] × CI(6)
Sampling time
2.2 V, 3 V
1000
ns
(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,
SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the
specified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5 MHz.
(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1
(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when
using the ADC12OSC divided by 2.
(4) The ADC12OSC is sourced directly from MODOSC inside the UCS.
(5) 13 × ADC12DIV × 1/fADC12CLK
(6) Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
12-Bit ADC, Linearity Parameters Using an External Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1.4 V ≤ dVREF ≤ 1.6 V(2)
VCC
MIN
TYP
MAX UNIT
±2
LSB
±1.7
Integral
EI
2.2 V, 3 V
linearity error(1)
(2)
1.6 V < dVREF
Differential
(2)
ED
2.2 V, 3 V
±1 LSB
linearity error(1)
dVREF ≤ 2.2 V(2)
dVREF > 2.2 V(2)
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
±3
±1.5
±1
±5.6
LSB
±3.5
EO
EG
ET
Offset error(3)
Gain error(3)
(2)
±2.5 LSB
dVREF ≤ 2.2 V(2)
dVREF > 2.2 V(2)
±3.5
±2
±7.1
LSB
±5
Total unadjusted
error
(1) Parameters are derived using the histogram method.
(2) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+ - VR-. VR+ < AVCC. VR-> AVSS.
Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω, and two decoupling capacitors,
10 µF and 100 nF, should be connected to VREF+/VREF- to decouple the dynamic current. See also the MSP430F5xx and
MSP430F6xx Family User's Guide (SLAU208).
(3) Parameters are derived using a best fit curve.
12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Integral linearity error(1)
Differential linearity error(1)
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
±1.7 LSB
±1 LSB
(2)
(2)
EI
See
See
2.2 V, 3 V
2.2 V, 3 V
ED
(1) Parameters are derived using the histogram method.
(2) AVCC as reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 0.
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