LP2987, LP2988
SNVS004J –MARCH 1999–REVISED APRIL 2013
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Figure 47. Plot of CDLY vs TDELAY
DETAILS OF ERR/RESET CIRCUIT OPERATION: (Refer to LP2987/8 Equivalent Circuit).
Figure 48. LP2987/8 Equivalent Circuit
The output of comparator U2 is the ERR/RESET flag. Since it is an open-collector output, it requires the use of a
pull-up resistor (RP). The 1.23V reference is tied to the inverting input of U2, which means that its output is
controlled by the voltage applied to the non-inverting input.
The output of U1 (also an open-collector) will force the non-inverting input of U2 to go low whenever the
LP2987/8 regulated output drops about 5% below nominal.
U1's inverting input is also held at 1.23V. The other input samples the regulated output through a resistive divider
(RA and RB). When the regulated output is at nominal voltage, the voltage at the divider tap point will be 1.23V. If
this voltage drops about 60 mV below 1.23V, the output of U1 will go low forcing the output of U2 low (which is
the ERROR state).
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