OBSOLETE
LMX2315, LMX2320, LMX2325
SNAS101E –SEPTEMBER 1996–REVISED MARCH 2013
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FUNCTIONAL DESCRIPTION
The simplified block diagram, Figure 22, below shows the 19-bit data register, the 14-bit R Counter and the S
Latch, and the 18-bit N Counter (intermediate latches are not shown). The data stream is clocked (on the rising
edge) into the DATA input, MSB first. If the Control Bit (last bit input) is HIGH, the DATA is transferred into the R
Counter (programmable reference divider) and the S Latch (prescaler select: LMX2315 and LMX2320: 64/65 or
128/129; LMX2325 32/33 or 64/65). If the Control Bit (LSB) is LOW, the DATA is transferred into the N Counter
(programmable divider).
Figure 22.
PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) AND PRESCALER SELECT (S LATCH)
If the Control Bit (last bit shifted into the Data Register) is HIGH, data is transferred from the 19-bit shift register
into a 14-bit latch (which sets the 14-bit R Counter) and the 1-bit S Latch (S15, which sets the prescaler: 64/65 or
128/129 for the LMX2315/20 or 32/33 or 64/65 for the LMX2325). Serial data format is shown below.
14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO(1)
Divide
S
14
S
13
S
12
S
11
S
10
S
9
S
8
S
7
S
6
S
5
S
4
S
3
S
2
S
1
Ratio
R
3
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
1
0
•
1
0
•
4
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(1) Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 16383
S1 to S14: These bits select the divide ratio of the programmable reference divider.
C: Control bit (set to HIGH level to load R counter and S Latch)
Data is shifted in MSB first.
Prescaler Select
S
15
LMX2315/20
128/129
64/65
LMX2325
64/65
32/33
0
1
12
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Product Folder Links: LMX2315 LMX2320 LMX2325
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