LM3881
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SNVS555C –JANUARY 2008–REVISED APRIL 2013
ENABLE CIRCUIT
The enable circuit is designed with an internal comparator, referenced to a bandgap voltage (1.22V), to provide a
precision threshold. This allows the timing to be set externally using a capacitor as shown in the diagram below.
Alternatively, sequencing can be based on a certain event such as a line voltage reaching 90% of its nominal
value by employing a resistor divider from VCC to Enable.
7 mA
EN
Enable
+
-
1.22V
CEN
Figure 14. Precision Enable Circuit
Using the internal pull-up current source to charge the external capacitor CEN, the time delay while the enable
voltage reaches the required threshold, assuming EN is charging from 0V, can be calculated by the equation as
follows.
1.22V x CEN
Tenable_delay
=
7 mA
EN
1.22V
0V
T
enable delay
Figure 15. Enable Delay Timing
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