SLLSEB6 – JULY 2012
demonstrate the switching behavior of the I
2
C isolator, ISO1540, between a master node at SDA1 and
a heavy loaded bus at SDA2
VCC2
VCC2
50%
30%
VCC1
VCC1
SDA2
SDA1
V
IHT1
transmit
delay
V
OL1
receive
delay
receive
delay
VCC1
receive
delay
VCC1
VCC2
transmit
delay
VCC2
V
IHT2
SDA1
50%
30%
SDA2
Figure 10. SDA Channel Timing in Receive and Transmit Directions
Receive Direction (left diagram)
When the I
2
C bus drives SDA2 low, SDA1 follows after a certain delay in the receive path. Its output low will be
the buffered output of V
OL1
= 0.75 V, which is sufficiently low to be detected by Schmitt-trigger inputs with a
minimum input-low voltage of V
IL
= 0.9 V at 3 V supply levels.
Once SDA2 is released, its voltage potential increases towards VCC2 following the time-constant formed by R
PU2
and C
bus
. After the receive delay, SDA1 is released and also rises towards VCC1, following the time-constant
R
PU1
x C
node
. Because of the significant lower time-constant, SDA1 may reach VCC1 before SDA2 reaches
VCC2 potential.
Transmit Direction (right diagram)
When a master drives SDA1 low, SDA2 follows after a certain delay in the transmit direction. When SDA2 turns
low it also causes the output of buffer B to turn low but at a higher 0.75 V level. This level cannot be observed
immediately as it is overwritten by the master’s lower low-level.
However, when the master releases SDA1, its voltage potential increases and first must pass the upper input
threshold of the comparator, V
IHT1
, to release SDA2. SDA1 then increases further until it reaches the buffered
output level of V
OL1
= 0.75 V, maintained by the receive path. Once comparator C turns high, SDA2 is released
after the delay in transmit direction. It takes another receive delay until B’s output turns high and fully releases
SDA1 to move towards VCC1 potential.
12
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