SLLSEB6 – JULY 2012
APPLICATION INFORMATION
I
2
C™ Bus Overview
The I
2
C (Inter-Integrated Circuit) bus is a single-ended, multi-master, 2-wire bus for efficient inter-IC
communication in half-duplex mode.
I
2
C uses open-drain technology, requiring two lines, Serial Data (SDA) and Serial Clock (SCL), to be connected
to VDD by resistors (see
Pulling the line to ground is considered a logic Zero while letting the line float
is a logic One. This is used as a channel access method. Transitions of logic states must occur while SCL is
Low, transitions while SCL is high indicate START and STOP conditions. Typical supply voltages are 3.3 V and 5
V, although systems with higher or lower voltages are permitted.
V
DD
R
PU
SDA
SCL
R
PU
R
PU
R
PU
R
PU
R
PU
R
PU
R
PU
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
GND
GND
GND
GND
μC
Master
ADC
Slave
DAC
Slave
μC
Slave
Figure 6. I
2
C BUS
I
2
C communication uses a 7-bit address space with 16 reserved addresses, so a theoretical maximum of 112
nodes can communicate on the same bus. In praxis, however, the number of nodes is limited by the specified,
total bus capacitance of 400 pF, which restricts communication distances to a few meters.
The specified signaling rates for the ISO1540 and ISO1541 are 100 kbps (Standard mode), 400 kbps (Fast
mode), 1 Mbps (Fast mode plus).
The bus has two roles for nodes: master and slave. A master node issues the clock, slave addresses, and also
initiates and ends data transactions. A slave node receives the clock and addresses and responds to requests
from the master.
shows a typical data transfer between master and slave.
7-bit
ADDRESS
8-bit
DATA
8-bit
DATA
ACK /
NACK
SDA
R/W
ACK
ACK
SCL
S
START
Condition
1 -7
8
9
1 -8
9
1 -8
9
P
STOP
condition
Figure 7. Timing Diagram of a Complete Data Transfer
The master initiates a transaction by creating a START condition, following by the 7-bit address of the slave it
wishes to communicate with. This is followed by a single Read/Write bit, representing whether the master wishes
to write to (0), or to read from (1) the slave. The master then releases the SDA line to allow the slave to
acknowledge the receipt of data.
The slave responds with an acknowledge bit (ACK) by pulling SDA low during the entire high time of the 9th
clock pulse on SCL, after which the master continues in either transmit or receive mode (according to the R/W bit
sent), while the slave continues in the complementary mode (receive or transmit, respectively).
10
Product Folder Link(s):
Copyright © 2012, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
