DS90CR285, DS90CR286
SNLS130C –MARCH 1999–REVISED MARCH 2013
www.ti.com
DS90CR285 DGG (TSSOP) Package Pin Description — Channel Link Transmitter
Pin Name
TxIN
I/O No.
Description
I
O
O
I
28 TTL level input.
TxOUT+
4
4
1
1
1
1
4
5
1
2
1
3
Positive LVDS differential data output.
Negative LVDS differential data output.
TxOUT−
TxCLK IN
TxCLK OUT+
TxCLK OUT−
PWR DWN
VCC
TTL IeveI clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
Positive LVDS differential clock output.
O
O
I
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down.
Power supply pins for TTL inputs.
I
GND
I
Ground pins for TTL inputs.
PLL VCC
I
Power supply pin for PLL.
PLL GND
LVDS VCC
LVDS GND
I
Ground pins for PLL.
I
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
I
DS90CR286 DGG (TSSOP) Package Pin Description — Channel Link Receiver
Pin Name
RxIN+
I/O No.
Description
I
I
4
4
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
RxIN−
RxOUT
O
I
28 TTL level data outputs.
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DWN
VCC
1
1
1
1
4
5
1
2
1
3
Positive LVDS differential clock input.
Negative LVDS differential clock input.
I
O
I
TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
TTL level input.When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
I
GND
I
Ground pins for TTL outputs.
PLL VCC
PLL GND
LVDS VCC
LVDS GND
I
Power supply for PLL.
I
Ground pin for PLL.
I
Power supply pin for LVDS inputs.
I
Ground pins for LVDS inputs.
14
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR285 DS90CR286
TI [ TEXAS INSTRUMENTS ]
