SNLS094D – JUNE 1998 – REVISED APRIL 2013
DS90C032 LVDS Quad CMOS Differential Line Receiver
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FEATURES
>155.5 Mbps (77.7 MHz) switching rates
Accepts small swing (350 mV) differential
signal levels
Ultra low power dissipation
600 ps maximum differential skew (5V, 25°C)
6.0 ns maximum propagation delay
Industrial operating temperature range
Military operating temperature range option
Available in surface mount packaging (SOIC)
and (LCCC)
Pin compatible with DS26C32A, MB570
(PECL), and 41LF (PECL)
Supports OPEN input fail-safe
Supports short and terminated input fail-safe
with the addition of external failsafe biasing
Compatible with IEEE 1596.3 SCI LVDS
standard
Conforms to ANSI/TIA/EIA-644 LVDS standard
Available to Standard Microcircuit Drawing
(SMD) 5962-95834
DESCRIPTION
TheDS90C032 is a quad CMOS differential line
receiver designed for applications requiring ultra low
power dissipation and high data rates. The device
supports data rates in excess of 155.5 Mbps (77.7
MHz) and uses Low Voltage Differential Signaling
(LVDS) technology.
TheDS90C032 accepts low voltage (350 mV)
differential input signals and translates them to
CMOS (TTL compatible) output levels. The receiver
supports a TRI-STATE function that may be used to
multiplex outputs. The receiver also supports OPEN,
shorted, and terminated (100Ω) input Failsafe with
the addition of external failsafe biasing. Receiver
output will be HIGH for both Failsafe conditions.
TheDS90C032
and
companion
line
driver
(DS90C031) provide a new alternative to high power
pseudo-ECL devices for high speed point-to-point
interface applications.
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Connection Diagram
Dual-In-Line
Figure 1. See Package Number D (R-PDSO-G16)
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PRODUCTION DATA information is current as of publication date.
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