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DRV8332DKDR 参数 Datasheet PDF下载

DRV8332DKDR图片预览
型号: DRV8332DKDR
PDF下载: 下载PDF文件 查看货源
内容描述: 三相PWM电机驱动器 [Three Phase PWM Motor Driver]
分类和应用: 驱动器运动控制电子器件信号电路光电二极管电动机控制电机PC
文件页数/大小: 31 页 / 1232 K
品牌: TI [ TEXAS INSTRUMENTS ]
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www.ti.com
SLES256 – MAY 2010
ELECTRICAL CHARACTERISTICS
T
A
= 25 °C, PVDD = 50 V, GVDD = VDD = 12 V, f
Sw
= 400 kHz, unless otherwise noted. All performance is in accordance
with recommended operating conditions unless otherwise specified.
PARAMETER
Internal Voltage Regulator and Current Consumption
V
REG
I
VDD
I
GVDD_X
I
PVDD_X
Output Stage
R
DS(on)
V
F
t
R
t
F
t
PD_ON
t
PD_OFF
t
DT
I/O Protection
V
uvp,G
V
uvp,hyst (1)
OTW
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage regulator, only used as a reference node
VDD supply current
VDD = 12 V
Idle, reset mode
Operating, 50% duty cycle
Reset mode
Operating, 50% duty cycle
Reset mode
2.95
3.3
9
10.5
1.7
8
0.7
3.65
12
V
mA
Gate supply current per half-bridge
Half-bridge X (A, B, or C) idle current
2.5
mA
1
mA
MOSFET drain-to-source resistance, low side (LS)
MOSFET drain-to-source resistance, high side (HS)
Diode forward voltage drop
Output rise time
Output fall time
Propagation delay when FET is on
Propagation delay when FET is off
Dead time between HS and LS FETs
T
J
= 25°C, GVDD = 12 V
T
J
= 25°C, GVDD = 12 V
T
J
= 25°C - 125°C, I
O
= 5 A
Resistive load, I
O
= 5 A
Resistive load, I
O
= 5 A
Resistive load, I
O
= 5 A
Resistive load, I
O
= 5 A
Resistive load, I
O
= 5 A
80
80
1
14
14
38
38
5.5
mΩ
mΩ
V
nS
nS
nS
nS
nS
Gate supply voltage GVDD_X undervoltage
protection threshold
Hysteresis for gate supply undervoltage event
Overtemperature warning
Hysteresis temperature to reset OTW event
Overtemperature shut down
OTE-OTW overtemperature detect temperature
difference
Hysteresis temperature for FAULT to be released
following an OTSD event
Overcurrent limit protection
Overcurrent response time
Resistor—programmable, nominal, R
OCP
= 27 kΩ
Time from application of short condition to Hi-Z of
affected FET(s)
115
8.5
0.8
125
25
150
25
25
9.7
250
135
V
V
°C
°C
°C
°C
°C
A
ns
OTW
hyst (1)
OTSD
(1)
OTE-
OTW
differential (1)
OTSD
HYST (1)
I
OC
I
OCT
Static Digital Specifications
V
IH
V
IH
V
IL
l
lkg
OTW / FAULT
R
INT_PU
V
OH
V
OL
Internal pullup resistance, OTW to VREG, FAULT to
VREG
High-level output voltage
Low-level output voltage
Internal pullup resistor only
External pullup of 4.7 kΩ to 5 V
I
O
= 4 mA
20
2.95
4.5
0.2
26
3.3
35
3.65
5
0.4
kΩ
V
V
High-level input voltage
High-level input voltage
Low-level input voltage
Input leakage current
PWM_A, PWM_B, PWM_C, M1, M2, M3
RESET_A, RESET_B, RESET_C
PWM_A, PWM_B, PWM_C, M1, M2, M3,
RESET_A, RESET_B, RESET_C
-100
2
2
3.6
3.6
0.8
100
V
V
V
mA
(1)
Specified by design
Copyright © 2010, Texas Instruments Incorporated
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