8.2.27 RMII Receive Timing
IDLE
(J/K)
Data
(TR)
Data
PMD Input Pair
T2.27.4
T2.27.5
X1
T2.27.1
T2.27.2
T2.27.2
T2.27.3
T2.27.2
RX_DV
CRS_DV
T2.27.2
RXD[1:0]
RX_ER
Parameter
Description
X1 Clock Period
Notes
Min Typ Max Units
T2.27.1
T2.27.2
50 MHz Reference Clock
20
ns
ns
RXD[1:0], CRS_DV, RX_DV
and RX_ER output delay from
X1 rising
2
14
T2.27.3
T2.27.4
T2.27.5
CRS ON delay
From JK symbol on PMD Receive Pair to
initial assertion of CRS_DV
18.5
27
bits
bits
bits
CRS OFF delay
From TR symbol on PMD Receive Pair to
initial deassertion of CRS_DV
RXD[1:0] and RX_ER latency From symbol on Receive Pair. Elasticity
buffer set to default value (01)
38
Note: Per the RMII Specification, output delays assume a 25pF load.
Note: CRS_DV is asserted asynchronously in order to minimize latency of control signals through the why. CRS_DV may
toggle synchronously at the end of the packet to indicate CRS deassertion.
Note: RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of
receive data.
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