8.2.5 100 Mb/s MII Receive Timing
T2.5.1
T2.5.1
RX_CLK
T2.5.2
RXD[3:0]
RX_DV
RX_ER
Valid Data
Parameter
T2.5.1
Description
RX_CLK High/Low Time
RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode
Notes
Min Typ Max Units
100 Mb/s Normal mode
16
10
20
24
30
ns
ns
T2.5.2
Note: RX_CLK may be held low or high for a longer period of time during transition between reference and recovered
clocks. Minimum high and low times will not be violated.
8.2.6 100BASE-TX Transmit Packet Latency Timing
TX_CLK
TX_EN
TXD
T2.6.1
IDLE
(J/K)
DATA
PMD Output Pair
Parameter
Description
Notes
Min
Typ Max
Units
T2.6.1
TX_CLK to PMD Output Pair 100 Mb/s Normal mode
Latency
6
bits
Note: For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after
the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100
Mb/s mode.
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