DCP01B SERIES
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SBVS012C − DECEMBER 2000 − REVISED AUGUST 2005
CON3
CON1
1
1
VS1
VS3
0S3
28
14
C1
SYNC
JP1
SYNC
C11
JP1
2
6
2
3
27
26
0V1
+V1
NC
13
12
14
+V3
C3
C2−1
C2
DCP02xU
R1
DCP02xP
C12
C13
R5
5
7
COM1
COM3
R2
C5
C4−1
C4
R6
C14
C15
−
V1
−
V3
CON2
SYNC
CON4
SYNC
1
1
2
VS4
0S4
VS2
0V2
28
27
26
14
JP2
C16
JP2
C6
2
3
NC
13
12
14
6
5
7
+V4
+V2
DCP02xU
DCP02xP
C17
R7
C18
C7
R3
C8
C7−1
COM4
COM2
R8
C20
C19
R4
C10
C9−1
C9
−
V4
−
V2
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
Capacitors C2−1, C4−1, C7−1, and C9−1 are through-hole plated components connected in parallel with C2, C4, C7 and C9 (1206 SMD), respectively.
For optimum low-noise performance, use low-ESR capacitors.
Do not connect the SYNC pin jumper (JP1−JP4) if the SYNC function is not being used.
Connections to the power input should be made with a minimum wire of 16/0.2 twisted pair, with the length kept short.
VSx and 0Vx are input supply and ground respecively (x represents the channel).
+Vx and −Vx are the positive and negative outputs, referenced to a common ground COMx.
JPx are the links used for self-synchronization; if this facility is not being used, the links should be unconnected.
R1−R8 are the power output loads; do not fit these if an external load is connected.
CON1 and CON2 are DIL-14; CON3 and CON4 are SO-28 packages.
NC = not connected.
Figure 7. Example of PCB Layout, Schematic Diagram
16
TI [ TEXAS INSTRUMENTS ]
