DAC7800
(Cont.)
DATA INPUT FORMAT
DAC7800 Digital Interface Block Diagram
UPD B
UPD A
DAC A Register
LSB
CLK
Data In
Bit
23
Bit
12
24-Bit
Shift Register
Bit
11
Bit
0
MSB
LSB
DAC B Register
MSB
DAC7800 Data Input Sequence
CLK
Data In
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 Bit 17 Bit 18 Bit 19 Bit 20
Bit 21 Bit 22 Bit 23
MSB
DAC B
LSB MSB
DAC B DAC A
LSB
DAC A
TIMING CHARACTERISTICS
V
DD
= +5V, V
REF A
= V
REF B
= +10V, T
A
= –40°C to +85°C.
t
5
PARAMETER
t
1
— Data Setup Time
t
2
— Data Hold Time
t
3
— Chip Select to CLK,
Update, Data Setup Time
t
4
— Chip Select to CLK,
Update, Data Hold Time
t
5
— CLK Pulse Width
t
6
— Clear Pulse Width
t
7
— Update Pulse Width
t
8
— CLK Edge to UPD A
or UPD B
MINIMUM
15ns
15ns
15ns
40ns
40ns
40ns
40ns
15ns
CLK
t
1
DATA
t
3
CS
t
8
UPD A
UPD B
CLR
NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. t
R
= t
F
= 5ns.
(2) Timing measurement reference level is V
IH
+ V
IL
.
2
t
7
t
4
t
2
0V
5V
0V
5V
5V
t
6
5V
4
DAC7800, 7801, 7802
www.ti.com
SBAS005A
TI [ TEXAS INSTRUMENTS ]
