AC PERFORMANCE
OUTPUT OP AMP IS OPA602.
At V
DD
= +5VDC, V
REF A
= V
REF B
= +10V, T
A
= +25°C, unless otherwise noted. These specifications are fully characterized but not subject to test.
DAC7800, 7801, 7802K
PARAMETER
OUTPUT CURRENT SETTLING TIME
DIGITAL-TO-ANALOG GLITCH IMPULSE
AC FEEDTHROUGH
OUTPUT CAPACITANCE
CHANNEL-TO-CHANNEL ISOLATION
V
REF A
to I
OUT B
CONDITIONS
To 0.01% of Full-Scale
R
L
= 100Ω, C
L
= 13pF
V
REF A
= V
REF B
= 0V
R
L
= 100Ω, C
L
= 13pF
f
VREF
= 10kHz
DAC Loaded with All 0s
DAC Loaded with All 1s
f
VREF A
= 10kHz
V
REF B
= 0V,
Both DACs Loaded with 1s
f
VREF B
= 10kHz
V
REF A
= 0V,
Both DACs Loaded with 1s
Full-Scale Transition
R
L
= 100Ω, C
L
= 13pF
–90
MIN
TYP
0.4
0.9
–75
30
70
–94
–72
50
100
✻
MAX
0.8
DAC7800, 7801, 7802L
MIN
TYP
✻
✻
✻
✻
✻
✻
✻
✻
✻
MAX
✻
UNITS
µs
nV-s
dB
pF
pF
dB
V
REF B
to I
OUT A
–90
–101
✻
✻
dB
DIGITAL CROSSTALK
0.9
✻
nV-s
✻
Same specification as for DAC7800, 7801, and 7802K.
NOTE: (1) Ensured but not tested.
DAC7800
BLOCK DIAGRAM
V
DD
12
DAC7800
Control Logic and Shift Register
12
DAC B Register
12
DAC B
Bit 0
Bit 11
Bit 12
Bit 23
DAC A
12
DAC A Register
12
5
8
7
Data
In
11
CLR
9
DGND
2
1
6
10
15
16
14
13
4
3
UPD B
I
OUT B
AGND B
R
FB B
V
REF B
V
REF A
R
FB A
I
OUT A
AGND A
UPD A
AGND A
I
OUT A
R
FB A
V
REF A
CLK
UPD A
Data In
CS
1
2
3
4
DAC7800
5
6
7
8
12
11
10
9
16
15
14
13
AGND B
I
OUT B
R
FB B
V
REF B
V
DD
CLR
UPD B
DGND
PIN CONFIGURATION
Top View
DIP
CLK CS
LOGIC TRUTH TABLE
CLK
X
X
X
X
X
UPD A
X
X
X
0
1
0
UPD B
X
X
X
1
0
0
CS
X
1
0
0
0
0
CLR
0
X
1
1
1
1
FUNCTION
All register contents set to 0’s (asynchronous).
No data transfer.
Input data is clocked into input register (location Bit 23) and previous data shifts.
Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A.
Input register bits 11 (LSB) - 0 (MSB) are loaded into DAC B.
Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A, and input register bits 11 (LSB) - 0 (MSB)
are loaded into DAC B.
X = Don’t care.
means falling edge triggered.
DAC7800, 7801, 7802
SBAS005A
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