DAC7801
BLOCK DIAGRAM
PIN CONFIGURATION
VDD
20
Top View
DIP
DAC7801
DAC A
MS
DAC A
LS
1
24
23
22
21
20
19
18
17
16
15
14
13
Input
Reg
Input
Reg
AGND A
AGND B
IOUT B
RFB B
VREF B
VDD
2
3
IOUT A
RFB A
VREF A
CS
4
8
DAC A Register
2
1
3
4
IOUT A
12
4
UPD
A1
AGND A
RFB A
19
16
15
5
DAC A
5
6
DB0
UPD
WR
A0
VREF A
DAC7801
7
DB1
CS
21 VREF B
22 RFB B
8
DB2
CLR
A1
WR
CLR
18
17
9
DB3
DAC B
12
23 IOUT B
24 AGND B
10
11
12
DB4
A0
DAC B Register
DB5
DB7
DB6
4
8
DAC B
MS
DAC B
LS
DGND
Input
Reg
Input
Reg
12
DGND
14
6
DB7–DB0
LOGIC TRUTH TABLE
CLR
UPD
CS
WR
A1
A0
FUNCTION
1
1
0
1
1
1
1
1
1
1
1
X
1
1
1
1
0
0
1
X
X
0
0
0
0
1
0
X
1
X
0
0
0
0
0
0
X
X
X
X
0
1
0
1
X
X
No Data Transfer
No Data Transfer
All Registers Cleared
X
X
0
0
1
1
X
X
DAC A LS Input Register Loaded with DB7 - DB0 (LSB)
DAC A MS Input Register Loaded with DB3 (MSB) - DB0
DAC B LS Input Register Loaded with DB7 - DB0 (LSB)
DAC B MS Input Register Loaded with DB3 (MSB) - DB0
DAC A, DAC B Registers Updated Simultaneously from Input Registers
DAC A, DAC B Registers are Transparent
X = Don’t care.
TIMING CHARACTERISTICS
VDD = +5V, VREF A = VREF B = +10V, TA = –40°C to +85°C.
t1
t2
5V
0V
A0–A1
t3
t4
5V
0V
PARAMETER
MINIMUM
DATA
t5
t6
t1 — Address Valid to Write Setup Time
t2 — Address Valid to Write Hold Time
t3 — Data Setup Time
10ns
10ns
30ns
10ns
0ns
0ns
40ns
40ns
5V
0V
CS, UPD
WR
t7
5V
0V
t4 — Data Hold Time
t5 — Chip Select or Update to Write Setup Time
t6 — Chip Select or Update to Write Hold Time
t7 — Write Pulse Width
t8
5V
0V
CLR
t8 — Clear Pulse Width
NOTES: (1) All input signal rise and fall times are measured from 10% to 90%
V
IH + VIL
of +5V. t R = t F = 5ns. (2) Timing measurement reference level is
.
2
DAC7800, 7801, 7802
5
SBAS005A
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TI [ TEXAS INSTRUMENTS ]
