AC PERFORMANCE
OUTPUT OP AMP IS OPA602.
At VDD = +5VDC, VREF A = VREF B = +10V, TA = +25°C, unless otherwise noted. These specifications are fully characterized but not subject to test.
DAC7800, 7801, 7802K
DAC7800, 7801, 7802L
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
OUTPUT CURRENT SETTLING TIME
To 0.01% of Full-Scale
0.4
0.8
ꢀ
ꢀ
µs
RL = 100Ω, CL = 13pF
DIGITAL-TO-ANALOG GLITCH IMPULSE
VREF A = VREF B = 0V
RL = 100Ω, CL = 13pF
0.9
ꢀ
ꢀ
nV-s
dB
AC FEEDTHROUGH
fVREF = 10kHz
–75
–72
ꢀ
OUTPUT CAPACITANCE
DAC Loaded with All 0s
DAC Loaded with All 1s
30
70
50
100
ꢀ
ꢀ
ꢀ
ꢀ
pF
pF
CHANNEL-TO-CHANNEL ISOLATION
VREF A to IOUT B
fVREF A = 10kHz
VREF B = 0V,
Both DACs Loaded with 1s
fVREF B = 10kHz
–90
–90
–94
ꢀ
ꢀ
ꢀ
ꢀ
dB
dB
VREF B to IOUT A
–101
VREF A = 0V,
Both DACs Loaded with 1s
DIGITAL CROSSTALK
Full-Scale Transition
0.9
ꢀ
nV-s
RL = 100Ω, CL = 13pF
ꢀ Same specification as for DAC7800, 7801, and 7802K.
NOTE: (1) Ensured but not tested.
DAC7800
BLOCK DIAGRAM
PIN CONFIGURATION
VDD
12
Top View
DIP
10 UPD B
15 IOUT B
16 AGND B
14 RFB B
12
DAC B Register
12
DAC7800
1
16
15
14
13
12
11
10
9
AGND A
AGND B
2
DAC B
IOUT A
IOUT B
RFB B
VREF B
VDD
Bit 0
3
RFB A
13 V REF B
Bit 11
4
VREF A
4
3
2
1
6
VREF A
RFB A
Bit 12
Bit 23
DAC7800
5
CLK
DAC A
6
UPD A
CLR
IOUT A
12
7
Data In
UPD B
DGND
DAC A Register
AGND A
UPD A
8
CS
12
5
8
7
11
9
DGND
Data
In
CLK CS
CLR
LOGIC TRUTH TABLE
CLK
UPD A UPD B
CS
CLR
FUNCTION
X
X
X
X
X
0
1
0
X
X
X
1
0
0
X
1
0
0
0
0
0
X
1
1
1
1
All register contents set to 0’s (asynchronous).
No data transfer.
Input data is clocked into input register (location Bit 23) and previous data shifts.
Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A.
Input register bits 11 (LSB) - 0 (MSB) are loaded into DAC B.
Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A, and input register bits 11 (LSB) - 0 (MSB)
are loaded into DAC B.
X
X
X
X = Don’t care.
means falling edge triggered.
DAC7800, 7801, 7802
3
SBAS005A
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