DIGITAL TIMING
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
Figure 3 and Table II provide detailed timing for the digital
interface of the DAC7613.
tRCS
tRDS
tRDH
tDZ
CS LOW for Read
R/W HIGH to CS LOW
R/W HIGH after CS HIGH
200
10
0
ns
ns
ns
ns
CS HIGH to Data Bus in
High Impedance
100
100
DIGITAL INPUT CODING
The DAC7613 input data is in Straight Binary format. The
output voltage is given by the following equation:
tCSD
tWCS
tWS
CS LOW to Data Bus Valid
CS LOW for Write
160
ns
ns
ns
ns
ns
ns
ns
ns
50
0
R/W LOW to CS LOW
R/W LOW after CS HIGH
Data Valid to CS LOW
Data Valid after CS HIGH
LOADDAC LOW
(1)
V
– VREFL • N
(
+
)
tWH
5
REFH
VOUT = VREFL
tDS
0
4096
tDH
5
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) or gain (full-scale)
errors.
tLWD
tRESET
50
50
RESET LOW
TABLE II. Timing Specifications (TA = –40°C to +85°C).
tWCS
CS
tWS
tWH
R/W
tRCS
tLWD
CS
tRDH
tRDS
LOADDAC
Data In
tDH
tDS
R/W
tDZ
Data Valid
Data Out
tRESET
tCSD
RESET
Data Output Timing
Digital Input Timing
FIGURE 3. Digital Input and Output Timing.
®
9
DAC7613