SNAS534B – MAY 1999 – REVISED MARCH 2013
Electrical Characteristics
V
REF
=10.000 V
DC
unless otherwise noted.
Boldface limits apply over temperature, T
MIN
≤T
A
≤T
MAX
.
(1)
For all other limits
T
A
=25°C.
Symbol
Parameter
Conditions
See
Note
V
CC
=15.75 V
DC
Typ
(2)
Tested
Limit
(3)
V
CC
=12 V
DC
±5%
to 15 V
DC
±5%
Design Limit
(4)
V
CC
=4.75 V
DC
Typ
(2)
Tested
Limit
(3)
V
CC
=5
V
DC
±5%
Design
Limit
(4)
Limit
Units
AC CHARACTERISTICS
(5)
t
s
t
W
Current Setting
Time
Write and XFER
Pulse Width Min
t
DS
Data Setup Time
Min
t
DH
Data Hold Time
Min
t
CS
Control Setup
Time
Min
t
CH
Control Hold Time
Min
(1)
(2)
(3)
(4)
(5)
V
IL
=0V, V
IH
=5V
See
(
1)
V
IL
=0V, V
IH
=5V
V
IL
=0V, V
IH
=5V
See
(
5)
1.0
100
250
320
100
250
320
320
320
1.0
375
600
900
375
600
900
50
50
600
320
10
0
900
1100
0
0
1100
900
900
μs
See
(
1)
V
IL
=0V, V
IH
=5V
See
(
1)
V
IL
=0V, V
IH
=5V
See
1)
(
30
30
ns
V
IL
=0V, V
IH
=5V
See
1)
(
110
250
320
0
0
0
Boldface
tested limits apply to the LJ and LCJ suffix parts only.
Typicals are at 25°C and represent most likely parametric norm.
Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
Ensured, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
The entire write pulse must occur within the valid data interval for the specified t
W
, t
DS
, t
DH
, and t
S
to apply.
Switching Waveform
Definition of Package Pinouts
Control Signals
(All control signals level actuated)
CS:
ILE:
Chip Select
(active low). The CS in combination with ILE will enable WR
1
.
Input Latch Enable
(active high). The ILE in combination with CS enables WR
1
.
WR
1
: Write 1.
The active low WR
1
is used to load the digital input data bits (DI) into the input latch. The data in
the input latch is latched when WR
1
is high. To update the input latch–CS and WR
1
must be low while ILE
Copyright © 1999–2013, Texas Instruments Incorporated
5
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