DAC0830, DAC0832
SNAS534B –MAY 1999–REVISED MARCH 2013
www.ti.com
There are several recommendations to minimize this effect. When latching data in the DAC, always use the input
register as the latch. Second, reducing the VCC supply for the DAC from +15V to +5V offers a factor of 5
improvement in the magnitude of the feedthrough, but at the expense of internal logic switching speed. Finally,
increasing CC (Figure 19) to a value consistent with the actual circuit bandwidth requirements can provide a
substantial damping effect on any output spikes.
Figure 16. Accommodating a High Speed System
ANALOG CONSIDERATIONS
The fundamental purpose of any D to A converter is to provide an accurate analog output quantity which is
representative of the applied digital word. In the case of the DAC0830, the output, IOUT1, is a current directly
proportional to the product of the applied reference voltage and the digital input word. For application versatility, a
second output, IOUT2, is provided as a current directly proportional to the complement of the digital input.
Basically:
where the digital input is the decimal (base 10) equivalent of the applied 8-bit binary word (0 to 255), VREF is the
voltage at pin 8 and 15 kΩ is the nominal value of the internal resistance, R, of the R-2R ladder network
(discussed in Section The Current Switching R-2R Ladder).
Several factors external to the DAC itself must be considered to maintain analog accuracy and are covered in
subsequent sections.
The Current Switching R-2R Ladder
The analog circuitry, Figure 17, consists of a silicon-chromium (SiCr or Si-chrome) thin film R-2R ladder which is
deposited on the surface oxide of the monolithic chip. As a result, there are no parasitic diode problems with the
ladder (as there may be with diffused resistors) so the reference voltage, VREF, can range −10V to +10V even if
VCC for the device is 5VDC
.
The digital input code to the DAC simply controls the position of the SPDT current switches and steers the
available ladder current to either IOUT1 or IOUT2 as determined by the logic input level (“1” or “0”) respectively, as
shown in Figure 17. The MOS switches operate in the current mode with a small voltage drop across them and
can therefore switch currents of either polarity. This is the basis for the 4-quadrant multiplying feature of this
DAC.
12
Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: DAC0830 DAC0832
TI [ TEXAS INSTRUMENTS ]
