DAC0830, DAC0832
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SNAS534B –MAY 1999–REVISED MARCH 2013
ILE=LOGIC “1”; WR2 and XFER GROUNDED
Figure 15.
Single-Buffered Operation
In a microprocessor controlled system where maximum data throughput to the DAC is of primary concern, or
when only one DAC of several needs to be updated at a time, a single-buffered configuration can be used. One
of the two internal registers allows the data to flow through and the other register will serve as the data latch.
Digital signal feedthrough (see Section Digital Signal Feedthrough) is minimized if the input register is used as
the data latch. Timing for this mode is shown in Figure 15.
Single-buffering in a “stand-alone” system is achieved by strobing WR1 low to update the DAC with CS, WR2 and
XFER grounded and ILE tied high.
Flow-Through Operation
Though primarily designed to provide microprocessor interface compatibility, the MICRO-DAC's can easily be
configured to allow the analog output to continuously reflect the state of an applied digital input. This is most
useful in applications where the DAC is used in a continuous feedback control loop and is driven by a binary up-
down counter, or in function generation circuits where a ROM is continuously providing DAC data.
Simply grounding CS, WR1, WR2, and XFER and tying ILE high allows both internal registers to follow the
applied digital inputs (flow-through) and directly affect the DAC analog output.
Control Signal Timing
When interfacing these MICRO-DAC to any microprocessor, there are two important time relationships that must
be considered to insure proper operation. The first is the minimum WR strobe pulse width which is specified as
900 ns for all valid operating conditions of supply voltage and ambient temperature, but typically a pulse width of
only 180ns is adequate if VCC=15VDC. A second consideration is that the specified minimum data hold time of
50ns should be met or erroneous data can be latched. This hold time is defined as the length of time data must
be held valid on the digital inputs after a qualified (via CS) WR strobe makes a low to high transition to latch the
applied data.
If the controlling device or system does not inherently meet these timing specs the DAC can be treated as a slow
memory or peripheral and utilize a technique to extend the write strobe. A simple extension of the write time, by
adding a wait state, can simultaneously hold the write strobe active and data valid on the bus to satisfy the
minimum WR pulsewidth. If this does not provide a sufficient data hold time at the end of the write cycle, a
negative edge triggered one-shot can be included between the system write strobe and the WR pin of the DAC.
This is illustrated in Figure 16 for an exemplary system which provides a 250ns WR strobe time with a data hold
time of less than 10ns.
The proper data set-up time prior to the latching edge (LO to HI transition) of the WR strobe, is insured if the WR
pulsewidth is within spec and the data is valid on the bus for the duration of the DAC WR strobe.
Digital Signal Feedthrough
When data is latched in the internal registers, but the digital inputs are changing state, a narrow spike of current
may flow out of the current output terminals. This spike is caused by the rapid switching of internal logic gates
that are responding to the input changes.
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