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SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008
PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER
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FEATURES
High-Performance 3:6 PLL-Based Clock
Synthesizer/Multiplier/Divider
User-Programmable PLL Frequencies
EEPROM Programming Without the Need to
Apply High Programming Voltage
Easy In-Circuit Programming via SMBus Data
Interface
Wide PLL Divider Ratio Allows 0-ppm Output
Clock Error
Clock Inputs Accept a Crystal, a Single-Ended
LVCMOS, or a Differential Input Signal
Accepts Crystal Frequencies From 8 MHz to
54 MHz
Accepts LVCMOS or Differential Input
Frequencies up to 200 MHz
Two Programmable Control Inputs [S0/S1,
A0/A1] for User-Defined Control Signals
Six LVCMOS Outputs With Output Frequencies
up to 300 MHz
LVCMOS Outputs Can Be Programmed for
Complementary Signals
Free Selectable Output Frequency via
Programmable Output Switching Matrix [6×6]
Including 7-Bit Post-Divider for Each Output
PLL Loop Filter Components Integrated
Low Period Jitter (Typically 60 ps)
Features Spread-Spectrum Clocking (SSC) for
Lowering System EMI
Programmable Output Slew-Rate Control
(SRC) for Lowering System EMI
3.3-V Device Power Supply
Industrial Temperature Range –40°C to 85°C
Development and Programming Kit for Easy
PLL Design and Programming (TI ClockPro
Software)
Packaged in 20-Pin TSSOP
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TERMINAL ASSIGNMENT
PW Package
(Top View)
S0/A0/CLK_SEL
S1/A1
V
CC
GND
CLK_IN0
CLK_IN1
V
CC
GND
SDATA
SCLOCK
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Y5
Y4
V
CCOUT2
GND
Y3
Y2
V
CCOUT1
GND
Y1
Y0
P0087-01
DESCRIPTION
The CDCE706 is one of the smallest and most
powerful PLL synthesizer/multiplier/dividers available
today. Despite its small physical outline, the
CDCE706 is very flexible. It has the capability to
produce an almost independent output frequency
from a given input frequency.
The input frequency can be derived from an
LVCMOS, differential input clock, or single crystal.
The appropriate input waveform can be selected via
the SMBus data interface controller.
To achieve an independent output frequency, the
reference divider M and the feedback divider N for
each PLL can be set to values from 1 to 511 for the
M-divider and from 1 to 4095 for the N-divider. The
PLL-VCO (voltage controlled oscillator) frequency
then is routed from the programmable output
switching matrix to any of the six outputs. The
switching matrix includes an additional 7-bit
post-divider (1 to 127) and an inverting logic for each
output.
The deep M/N divider ratio allows the generation of
zero-ppm clocks from any reference input frequency
(e.g., 27 MHz).
The CDCE706 includes three PLLs; of those, one
supports spread-spectrum clocking (SSC). PLL1,
PLL2, and PLL3 are designed for frequencies up to
300 MHz and optimized for zero-ppm applications
with wide divider factors.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2008, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
