CDCE706
www.ti.com ........................................................................................................................................... SCAS815I–OCTOBER 2005–REVISED NOVEMBER 2008
DEVICE CHARACTERISTICS (continued)
over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1
PARAMETER
TEST CONDITIONS
MIN
80
TYP(1)
MAX UNIT
All PLLs
200
Normal speed-mode(3)
VCO frequency of internal PLL (any of three
PLLs)
fVCO
PLL2 with SSC
80
167
300
250
300
MHz
MHz
High-speed mode(3)
VCC = 2.5 V
180
LVCMOS output frequency range(4), See
Figure 4
fOUT
VCC = 3.3 V
LVCMOS PARAMETER
VIK
LVCMOS input voltage
VCC = 3 V, II = –18 mA
–1.2
±5
V
LVCMOS input current (CLK_IN0 and
CLK_IN1)
II
VI = 0 V or VCC, VCC = 3.6 V
µA
IIH
IIL
LVCMOS input current (S1/S0)
LVCMOS input current (S1/S0)
VI = VCC, VCC = 3.6 V
VI = 0 V, VCC = 3.6 V
5
µA
µA
–35
–10
Input capacitance at CLK_IN0 and
CLK_IN1
CI
VI = 0 V or VCC
3
pF
LVCMOS PARAMETER FOR VCCOUT = 3.3-V Mode
VCCOUT = 3 V, IOH = –0.1 mA
VCCOUT = 3 V, IOH = –4 mA
VCCOUT = 3 V, IOH = –6 mA
VCCOUT = 3 V, IOL = 0.1 mA
VCCOUT = 3 V, IOL = 4 mA
VCCOUT = 3 V, IOL = 6 mA
All PLL bypass
2.9
2.4
2.1
VOH
LVCMOS high-level output voltage
V
0.1
0.5
VOL
LVCMOS low-level output voltage
Propagation delay
V
0.85
9
11
tPLH
,
ns
tPHL
VCO bypass
tr0/tf0
tr1/tf1
tr2/tf2
Rise and fall time for output slew rate 0
Rise and fall time for output slew rate 1
Rise and fall time for output slew rate 2
VCCOUT = 3.3 V (20%–80%)
VCCOUT = 3.3 V (20%–80%)
VCCOUT = 3.3 V (20%–80%)
1.7
1.5
1.2
3.3
2.5
1.6
4.8
3.2
2.1
ns
ns
ns
Rise and fall time for output slew rate 3
(default configuration)
tr3/tf3
VCCOUT = 3.3 V (20%–80%)
0.4
0.6
1
ns
fOUT = 50 MHz
55
45
90
80
1 PLL, 1 output
3 PLLs, 3 outputs
1 PLL, 1 output
3 PLLs, 3 outputs
fOUT = 245.76 MHz
fOUT = 50 MHz
tjit(cc)
Cycle-to-cycle jitter(5)(6)
ps
125
60
155
95
fOUT = 245.76 MHz
fOUT = 50 MHz
60
90
fOUT = 245.76 MHz
fOUT = 50 MHz
55
80
tjit(per) Peak-to-peak period jitter(5)(6)
ps
ps
145
70
180
105
fOUT = 245.76 MHz
1.6-ns rise/fall time at fVCO = 150 MHz,
Pdiv = 3
tsk(o)
odc
Output skew (see(7) and Table 5)
Output duty cycle(8)
200
fVCO = 100 MHz, Pdiv = 1
45%
55%
(3) Normal-speed mode or high-speed mode must be selected by the VCO frequency selection bit in byte 6, bits [7:5]. The minimum fVCO
can be lower, but impacts jitter performance.
(4) Do not exceed the maximum power dissipation of the 20-pin TSSOP package (600 mW at no air flow).
(5) 50,000 cycles
(6) Jitter depends on configuration. Jitter data is normal tr/tf, input frequency = 3.84 MHz, fVCO = 245.76 MHz.
(7) The tsk(o) specification is only valid for equal loading of all outputs.
(8) odc depends on output rise and fall time (tr/tf). The data is for normal tr/tf and is valid for both SSC on and off.
Copyright © 2005–2008, Texas Instruments Incorporated
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