CC2510Fx / CC2511Fx
The packet control hardware therefore
automatically inserts one or two extra bytes at
the end of the packet, so that the total length
of the data to be interleaved is an even
number. Note that these extra bytes are
invisible to the user, as they are removed
before the received packet enters the RFD
data register.
CC2510Fx/CC2511Fx employs matrix interleaving,
which is illustrated in Figure 53. The on-chip
interleaving and de-interleaving buffers are 4 x
4 matrices. In the transmitter, the data bits
from the rate ½ convolutional coder are written
into the rows of the matrix, whereas the bit
sequence to be transmitted is read from the
columns of the matrix. Conversely, in the
receiver, the received symbols are written into
the rows of the matrix, whereas the data
passed onto the convolutional decoder is read
from the columns of the matrix.
When FEC and interleaving is used the
minimum data payload is 2 bytes.
Note:
When
using
FEC
When FEC and interleaving is used at least
one extra byte is required for trellis
termination. In addition, the amount of data
transmitted over the air must be a multiple of
the size of the interleaver buffer (two bytes).
(MDMCFG1.FEC_EN=1), CLKCON.CLKSPD
must be set to 000.
Interleaver
Write buffer
Interleaver
Read buffer
Packet
Engine
FEC
Encoder
Modulator
Interleaver
Write buffer
Interleaver
Read buffer
FEC
Decoder
Packet
Engine
Demodulator
Figure 53: General Principle of Matrix Interleaving
13.12 Radio Control
A simplified state diagram is shown in Figure
48 on Page 184. The complete radio control
state diagram is shown in Figure 54. The
numbers refer to the state number readable in
the MARCSTATEstatus register. This register is
primarily for test purposes.
CC2510Fx/CC2511Fx has a built-in state machine
that is used to switch between different
operation states (modes). The change of state
is done either by using command strobes or by
internal events such as TX FIFO underflow.
SWRS055F
Page 198 of 241
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