CC2510Fx / CC2511Fx
register, the CPU interrupt flag S1CON.RFIF
will also be asserted in addition to the interrupt
flag in RFIF. If IEN2.RFIE=1 when
S1CON.RFIF is asserted, and interrupt
request will be generated.
• Packet received/transmitted. Also used
to detect overflow/underflow conditions
• CS
• PQT reached
• CCA
Refer to 1.1 for details about the interrupts.
• SFD
Each of these events has a corresponding
interrupt flag in the RFIF register which is
asserted when the event occurs. If the
corresponding mask bit is set in the RFIM
RFIF (0xE9) - RF Interrupt Flags
Bit
Field Name
Reset
R/W
Description
7
IRQ_TXUNF
0
R/W0
TX underflow
0
1
No interrupt pending
Interrupt pending
6
5
4
IRQ_RXOVF
IRQ_TIMEOUT
IRQ_DONE
0
0
0
R/W0
R/W0
R/W0
RX overflow
0
1
No interrupt pending
Interrupt pending
RX timeout, no packet has been received in the programmed period
0
1
No interrupt pending
Interrupt pending
Packet received/transmitted. Also used to detect underflow/overflow
conditions
0
1
No interrupt pending
Interrupt pending
3
2
1
0
IRQ_CS
0
0
0
0
R/W0
R/W0
R/W0
R/W0
Carrier sense
0
1
No interrupt pending
Interrupt pending
IRQ_PQT
IRQ_CCA
IRQ_SFD
Preamble quality threshold reached
0
1
No interrupt pending
Interrupt pending
Clear Channel Assessment
0
1
No interrupt pending
Interrupt pending
Start of Frame Delimiter, sync word detected
0
1
No interrupt pending
Interrupt pending
SWRS055F
Page 186 of 241
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