CC2510Fx / CC2511Fx
An isochronous data packet in the OUT FIFO
may have bit errors. The hardware will detect
this condition and set USBCSOL.DATA_ERROR.
Firmware should therefore always check this
bit when unloading a data packet.
The word size can be byte (8 bits) or word (16
bits). When word size transfer is used the
ENDIAN register must be set correctly (see
Section 12.5.7). The ENDIAN.USBRLE bit
selects whether a word is read as little or big
endian from the OUT FIFOs and the
ENDIAN.USBWLEbit selects whether a word is
written as little or big endian to the IN FIFOs.
Writing and reading words for the different
settings is shown in Figure 45 and Figure 46
respectively. Notice that the setting for these
bits will be used for all endpoints.
Consequently, it is not possible to have
multiple DMA channels active at once that use
different endianess. The ENDIANregister must
be configured to use big endian for both read
and write for a word size transfer to produce
the same result as a byte size transfer of an
even number of bytes. Word size transfers are
slightly more efficient than byte transfers.
The AutoClear feature will typically not be used
for isochronous endpoints since the packet
size will increase or decrease from frame to
frame.
12.16.7 DMA
DMA should be used to fill the IN endpoint
FIFOs and empty the OUT endpoint FIFOs.
Using DMA will improve the read/write
performance significantly compared to using
the 8051 CPU. It is therefore highly
recommended to use DMA unless timing is not
critical or only a few bytes are to be
transferred.
Refer to Section 12.5 for more details
regarding DMA.
There are no DMA triggers for the USB
controller, meaning that DMA transfers must
be triggered by firmware.
Figure 45: Writing Big/Little Endian
Figure 46: Reading Big/Little Endian
SWRS055F
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