bq3285ED/LD
Read/Write Timing—bq3285LD (TA = TOPR, VCC = 3V)
Symbol
tCYC
tDSL
tDSH
tRWH
tRWS
tCS
Parameter
Minimum
Typical
Maximum
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Cycle time
270
135
90
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DS low or RD/WR high time
DS high or RD/WR low time
R/W hold time
-
-
R/W setup time
15
8
-
Chip select setup time
Chip select hold time
Read data hold time
-
tCH
0
-
tDHR
tDHW
tAS
0
40
-
Write data hold time
Address setup time
0
30
15
15
50
55
-
tAH
Address hold time
-
tDAS
tASW
tASD
Delay time, DS to AS rise
Pulse width, AS high
Delay time, AS to DS rise (RD/WR fall)
-
-
-
Output data delay time from DS rise
(RD fall)
tOD
-
-
100
ns
tDW
tBUC
tPI
Write data setup time
50
-
-
244
-
-
-
-
-
ns
µs
-
Delay time before update cycle
Periodic interrupt time interval
Time of update cycle
-
See Table 3
tUC
-
1
µs
July 1997
18