SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012
ELECTRICAL CHARACTERISTICS (Continued)
FET DRIVE CIRCUIT, T
A
= 25°C, CREG = 1
μF,
C
L
= 2.2
μF,
VCC or BAT = 14 V (unless otherwise noted)
PARAMETER
V
O(FETOND)
= V
(DSG)
– Vpack
VGS connect 10 MΩ
V
O(FETONC)
= V
(CHG)
– V
BAT
VGS connect 10 MΩ
BAT = 4.5 V
VFETOND = VDSG –
Vpack
VFETONC = VCHG – VBAT
C
L
= 4700 pF
C
L
= 4700 pF
V
(CHG)
:
V
(DSG)
:
V
(CHG)
:
V
(DSG)
:
Vpack
≥
Vpack + 4 V
VBAT
≥
VBAT + 4 V
Vpack + VCHG (FETON)
≥
pack + 1 V
VC1 + VDSG (FETON)
≥
VC1 + 1 V
400
400
40
40
TEST CONDITIONS
T
A
= 25°C
T
A
= –40°C to 110°C
T
A
= 25°C
T
A
= –40°C to 110°C
MIN
7.5
8
7.5
8
3.3
TYP
12
12
12
12
3.5
MAX
15.5
16
15.5
16
3.7
0.2
V
0.2
1000
1000
200
200
μs
UNIT
V
V
O(FETON)
Output voltage, charge,
and discharge FETs on
V
V
V
(ZCHG)
V
O(FETOF
F)
ZVCHG clamp voltage
Output voltage, charge,
and discharge FETs off
t
r
t
f
Rise time
Fall time
μs
LOGIC, T
A
= 25°C, CREG = 1
μF,
C
L
= 2.2
μF,
VCC or BAT = 14 V (unless otherwise noted)
XALERT
R
(PUP)
Internal pullup resistance SDATA, SCLK
XRST
XALERT
SDATA, I
OUT
= 200
μA
V
OL
Low Logic level output
voltage
GPOD, I
OUT
= 50
μA
VCC or BAT = 7 V,
VREG = 1.5 V,
XRST, I
OUT
= 200
μA
Hysteresis
450
T
A
= –40°C to 110°C
T
A
= –40°C to 110°C
60
6
1
100
10
3
200
20
6
0.2
0.4
0.6
0.4
V
kΩ
V
IH
SCLK (hysteresis input)
mV
AC ELECTRICAL CHARACTERISTICS
T
A
= 25°C, CREG = 1
μF,
C
L
= 2.2
μF,
VCC or BAT = 14 V (unless otherwise noted)
PARAMETER
t
WDTINT
t
WDWT
t
RST
WDT start up detect time
WDT detect time
XRST Active high time
TEST CONDITIONS
MIN
250
50
100
TYP
500
100
250
MAX
1000
150
560
UNIT
ms
μs
μs
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