bq29330
SLUS673E –SEPTEMBER 2005–REVISED MARCH 2012
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AC TIMING REQUIREMENTS (I2C compatible serial interface)
TA = 25°C, CREG = 1 μF, VCC or BAT = 14 V (unless otherwise noted)
PARAMETER
MIN
MAX
1000
300
UNIT
ns
tr
SCLK, SDATA rise time
tf
SCLK, SDATA fall time
ns
tw(H)
SCLK pulse width high
4
4.7
4.7
4
μs
tw(L)
SCLK pulse width low
μs
tsu(STA)
th(STA)
tsu(DAT)
th(DAT)
tsu(STOP)
tsu(BUF)
tv
Setup time for start condition
Start condition hold time after which first clock pulse is generated
Data setup time
μs
μs
250
0
ns
Data hold time
μs
Setup time for Stop condition
Time the bus must be free before new transmission can start
Clock low to data out valid
4
μs
4.7
μs
900
100
ns
th(CH)
fSCL
Data out hold time after clock low
Clock frequency
10
0
ns
kHz
t
t
f
t
r
su(STA)
t
t
w(L)
w(H)
SCLK
t
r
t
f
SDATA
Start
Stop
SDA
Input
SDA
Change
Condition
Condition
t
h(ch)
t
t
h(DAT)
su(DAT)
t
h(STA)
1
2
3
7
8
9
SCLK
MSB
ACK
SDATA
Start Condition
t
v
t
su(STOP)
SCLK
1
2
3
7
8
9
t
su(BUF)
MSB
SDATA
ACK
Stop Condition
10
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