SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012
PIN FUNCTIONS (continued)
PIN
NAME
WDI
SCLK
SDATA
XALERT
NC
DBT NO.
26
28
29
30
15,18,27
RSM NO.
24
25
26
27
2, 10, 12,
14, 20
DESCRIPTION
Digital input that provides the timing clock for the OC and SC delays and also acts as the watchdog
clock.
Open-drain serial interface clock with internal 10-kΩ pullup to V
REG
Open-drain bidirectional serial interface data with internal 10-kΩ pullup to V
REG
Open-drain output used to indicate status register changes. With internal 100-kΩ
pullup to V
REG
Not electrically connected to the IC
FUNCTIONAL BLOCK DIAGRAM
GG VDD
PACK–
R
ZVCHG
PACK+
GG RST
C
2nd
Protection
REG
PACK
DSG
CHG
ZVCHG
VCC
REG
RST
GG LED
INPUT
C
BAT
VC1
VC2
CELL 4
CELL 3
CELL 2
CELL 1
LEDOUT
CHG_ON
PMS
NCH GATE
DRIVER
DSG_ON
FET
LOGIC
ZVCHG_ON
GATE DRIVER
3.3-V LDO
2.5-V LDO
POR
LED
32 kHz INPUT
FROM GG
WDI
WATCHDOG
TIMER
SHIP_ON
SLEEP_ON
POWER
MODE
CIRCUIT
CELL1..4
CELL
SELECTION
SWITCHES
VC3
VC4
VC5
SERIAL INTERFACE
REGISTERS
STATUS
OUTPUT CTL
STATE CTL
FUNCTION CTL
CELL SEL
OLV
OLD
SCC
SCD
0.975V
BAT/25
PACK/25
GG INTERFACE
SDATA
GG INTERFACE
SCLK
SDATA
CELL+
CELL VOLTAGE
TRANSLATION
CELL–
R
C
CELL
GG ANALOG
INPUT
GG TS
INPUT
C
THERM
SCLK
XALERT
ALERT TO GG
OPEN DRAIN
OUTPUT
GPOD
OPEN
DRAIN
OUTPUT
DRIVE
CONTROL
OVERLOAD
-
COMPARATOR
OVERCURRENT
TOUT
THERM
GND
THERMISTOR
SRP
R
SRN
DELAY
SHORT CIRCUIT
COMPARATOR
SHORT_CIRCUIT
SNS
4
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