bq24296
bq24297
SLUSBP6A –SEPTEMBER 2013–REVISED OCTOBER 2013
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ELECTRICAL CHARACTERISTICS (continued)
VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values unless other
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
BOOST MODE OPERATION
VOTG_REG_ACC
VOTG_REG_ACC
VOTG_BAT
OTG output voltage
I(VBUS)=0, REG06[7:4]=0111 (4.998V)
I(VBUS) = 0, REG06[7:4]=0111 (4.998V)
BAT falling, REG04[1]=1
REG01[0] = 0
5
V
OTG output voltage accuracy
Battery voltage exiting OTG mode
-3
2.9
1
3
%
V
A
IOTG
OTG mode output current
REG01[0] = 1
1.5
5.8
A
VOTG_OVP
OTG over-voltage threshold
Rising Threshold
6
V
VOTG_OVP_HYS
IOTG_LSOCP
IOTG_HSZCP
OTG over-voltage threshold hysteresis
LSFET cycle by cycle current limit
HSFET under current falling threshold
Falling Threshold
300
mV
A
5
100
1.15
1.70
mA
REG01[0] = 0
REG01[0] = 1
1.00
1.50
1.30
1.90
IRBFET_OCP
RBFET over-current threshold
A
OTG mode over-current protection off cycle
time
tOTG_OCP_OFF
32
ms
µs
OTG mode over-current protection on cycle
time
tOTG_OCP_ON
260
REGN LDO
VVBUS = 6V, IREGN = 40mA
VVBUS = 5V, IREGN = 20mA
VVBUS = 5V, VREGN = 3.8V
4.8
4.7
50
5
5.5
V
V
VREGN
REGN LDO output voltage
REGN LDO current limit
4.8
IREGN
mA
QON Timing
tQON
QON pin high time to turn on BATFET
2
ms
LOGIC I/O PIN CHARACTERISTICS (OTG, CE, STAT, QON, PSEL, PG)
VILO
Input low threshold
0.4
V
V
V
VIH
Input high threshold
1.3
VOUT_LO
Output low saturation voltage
Sink current = 5 mA
Pull up rail 1.8V
Pull up rail 3.6V
0.4
1
High level leakage current (OTG, CE,
STAT , PSEL, PG)
IBIAS
µA
µA
IBIAS
High level leakage current (QON)
8
I2C INTERFACE (SDA, SCL, INT)
VIH
Input high threshold level
VPULL-UP = 1.8V, SDA and SCL
VPULL-UP = 1.8V, SDA and SCL
Sink current = 5mA
1.3
V
V
VIL
Input low threshold level
Output low threshold level
High-level leakage current
SCL clock frequency
0.4
0.4
1
VOL
IBIAS
fSCL
V
VPULL-UP = 1.8V, SDA and SCL
µA
kHz
400
DIGITAL CLOCK AND WATCHDOG TIMER
fHIZ
fDIG
Digital crude clock
Digital clock
REGN LDO disabled
REGN LDO enabled
REGN LDO disabled
REGN LDO enabled
15
1300
112
35
1500
160
50
kHz
kHz
1700
tWDT
REG05[5:4]=11
sec
136
160
12
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