ADS8284
SLAS628–MARCH 2009................................................................................................................................................................................................... www.ti.com
ANALOG INPUT
The device features an analog multiplexer, a differential, high input impedance, unity gain ADC driver, and a high
performance ADC. Typically alot of care is required for driving circuit component selection and board layout for
high resolution ADC driving. However an on-board ADC driver simplifies the job for the user. All that is required
is to decouple AINP and AINM with a 1-nF decoupling capacitor across these two terminals as close to the
device as possible. The multiplexer inputs tolerate source impedance of up to 50 Ω for specified device
performance at an operating speed of 1-MSPS. This relaxes constraints on the signal conditioning circuit. In the
case of true bipolar input signals, it is possible to condition them with a resister divider as shown in Figure 71.
The device permits use of 1.2-kΩ resistors for the divider with effective source impedance of 600 Ω for signal
bandwidth less than 10 kHz. A suitable capacitor value used to limit signal bandwidth limits noise coming from
the resistor divider network. Care must be taken concerning absolute analog voltage at the multiplexer input
terminals. This voltage should not exceed VCC and VEE. The clamp at the driver OPA limits the voltage applied
to the ADC input.
Reading Data
The ADS8284 outputs full parallel data in straight binary format as shown in Table 3. The parallel output is active
when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST.
This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should attempted
within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE and BUS18/16
are used for multiword read operations. BYTE is used whenever lower bits on the bus are output on the higher
byte of the bus. BUS18/16 is used whenever the last two bits on the 18-bit bus is output on either bytes of the
higher 16-bit bus. Refer to Table 3 for ideal output codes.
Table 3. Ideal Input Voltages and Output Codes
DESCRIPTION
Full scale range
ANALOG VALUE
2 × (+Vref
DIGITAL OUTPUT STRAIGHT BINARY
)
Least significant bit (LSB)
+Full scale
2 × (+Vref)/262144
(+Vref) – 1 LSB
0 V
BINARY CODE
HEX CODE
1FFFF
01 1111 1111 1111 1111
00 0000 0000 0000 0000
11 1111 1111 1111 1111
10 0000 0000 0000 0000
Midscale
00000
Midscale – 1 LSB
Zero
0 V – 1 LSB
–Vref
3FFFF
20000
The output data is a full 18-bit word (D17–D0) on DB17–DB0 pins (MSB–LSB) if both BUS18/16 and BYTE are
low.
The result may also be read on an 16-bit bus by using only pins DB17–DB2. In this case two reads are
necessary: the first as before, leaving both BUS18/16 and BYTE low and reading the 16 most significant bits
(D17–D2) on pins DB17–DB2, then bringing BUS18/16 high while holding BYTE low. When BUS18/16 is high,
the lower two bits (D1–D0) appear on pins DB3–DB2.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB17–DB10. In this
case three reads are necessary: the first as before, leaving both BUS18/16 and BYTE low and reading the 8
most significant bits on pins DB17–DB10, then bringing BYTE high while holding BUS18/16 low. When BYTE is
high, the medium bits (D9–D2) appear on pins DB17–DB10. The last read is done by bringing BUS18/16 high
while holding BYTE high. When BUS18/16 is high, the lower two bits (D1–D0) appear on pins DB11–DB10. The
last read cycle is not necessary if only the first 16 most significant bits are of interest.
All of these multiword read operations can be performed with multiple active RD (toggling) or with RD held low
for simplicity. This is referred to as the AUTO READ operation.
Table 4. Conversion Data Read Out
DATA READ OUT
BYTE
BUS18/16
PINS
PINS
PINS
PINS
PINS
DB17–DB12
DB11–DB10
DB9–DB4
DB3–DB2
DB1–DB0
High
Low
High
High
All One's
All One's
D1–D0
All One's
All One's
All One's
D1–D0
All One's
All One's
All One's
30
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