Mode II (M0 = 0, M1 = 1)
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections
and digital inputs that occur just prior to latching the output
of the analog comparator. Thus, driving any single conver-
sion for an n-bit SAR converter, there are n “windows” in
which large external transient voltages can affect the conver-
sion result. Such glitches might originate from switching
power supplies, nearby digital logic or high power devices.
The degree of error in the digital output depends on the
reference voltage, layout, and the exact timing of the exter-
nal event. Their error can change if the external event
changes in time with respect to the CLOCK input.
With M1 set to ‘1’, the ADS7861 will output data on the
Serial Data A pin only. All other pins function in the same
manner as Mode I except that the Serial Data B output will
tri-state (i.e., high impedance) after a conversion following
M1 going HIGH. Another difference in this mode involves
the CONVST pin. Since it takes 32 clock cycles to output
the results from both A/D converters (rather than 16 when
M1 = 0), the ADS7861 will take 4µs to complete a
conversion on both A/Ds (See Figure 11).
Mode III (M0 = 1, M1 = 0)
With M0 set to ‘1’, the ADS7861 will cycle through Chan-
nels 0 and 1 sequentially (the A0 pin is ignored). At the same
time, setting M1 to ‘0’ places both Serial Outputs, A and B,
in the active mode (See Figure 12).
With this in mind, power to the ADS7861 should be clean
and well-bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1µF to 10µF capacitor is recommended. If needed, an even
larger capacitor and a 5Ω or 10Ω series resistor may be used
to low pass filter a noisy supply. On average, the ADS7861
draws very little current from an external reference as the
reference voltage is internally buffered. However, glitches
from the conversion process appear at the VREF input and the
reference source must be able to handle this. Whether the
reference is internal or external, the VREF pin should be
bypassed with a 0.1µF capacitor. An additional larger ca-
pacitor may also be used, if desired. If the reference voltage
is external and originates from an op amp, make sure that it
can drive the bypass capacitor or capacitors without oscilla-
tion. No bypass capacitor is necessary when using the
internal reference (tie pin 10 directly to pin 11).
Mode IV (M0 = 1, M1 = 1)
Similar to Mode II, Mode IV uses the Serial A output line to
transmit data exclusively. Following the first conversion
after M1 goes HIGH, the serial B output will go into tri-
state. See Figure 13. As in Mode II, the second CONVST
command is always ignored when M1 = 1.
READING DATA
In all four timing diagrams, the CONVST pin and the RD
pins are tied together. If so desired, the two lines can be
separated. Data on the Serial Output pins (A and B) will
become valid following the third rising SCLK edge follow-
ing RD rising edge. Refer to Table II for data output format.
The GND pin should be connected to a clean ground point.
In many cases, this will be the ‘analog’ ground. Avoid
connections which are too near the grounding point of a
microcontroller or digital signal processor. If required, run a
ground trace directly from the converter to the power supply
entry point. The ideal layout will include an analog ground
plane dedicated to the converter and associated analog
circuitry.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7861 circuitry. This is particu-
larly true if the CLOCK input is approaching the maximum
throughput rate.
ADS7861
12
SBAS110D
TI [ TEXAS INSTRUMENTS ]
