HIGH within this window, it is then uncertain as to when the
ADS7861 will initiate conversion (see Figure 8 for a more
detailed description). Sixteen clock cycles are required to
perform a single conversion. Immediately following
CONVST switching to HIGH, the ADS7861 will switch
from the sample mode to the hold mode asynchronous to the
external clock. The BUSY output pin will then go HIGH and
remain HIGH for the duration of the conversion cycle. On
the falling edge of the first cycle of the external clock, the
ADS7861 will latch in the address for the next conversion
cycle depending on the status of the A0 pin (HIGH =
Channel 1, LOW = Channel 0). The address must be selected
15ns prior to the falling edge of cycle one of the external clock
and must remain ‘held’ for 15ns following the clock edge. For
maximum throughput time, the CONVST and RD pins should
be tied together. CS must be brought LOW to enable the two
serial outputs. Data will be valid on the falling edge of all 16
clock cycles per conversion. The first bit of data will be a
status flag for either Channel 0 or 1, the second bit will be a
second status flag for either Channel A or B. The subsequent
data will be MSB-first through the LSB, followed by two
zeros (see Table II and Figures 9 and 10).
tCKP
125ns
CLOCK
Cycle 1
Cycle 2
10ns
10ns
5ns
5ns
B
CONVST
A
C
NOTE: All CONVST commands which occur more than 10ns before the rising edge of cycle ‘1’ of the external clock
(Region ‘A’) will initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands which occur 5ns after
the rising edge of cycle ‘1’ or 10ns before the rising edge of cycle 2 (Region ‘B’) will initiate a conversion on the
rising edge of cycle ‘2’. All CONVST commands which occur 5ns after the rising edge of cycle ‘2’ (Region ‘C’) will
initiate a conversion on the rising edge of the next clock period. The CONVST pin should never be switched from
LOW to HIGH in the region 10ns prior to the rising edge of the CLOCK and 5ns after the rising edge (gray areas). If
CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or
the following edge.
FIGURE 8. Conversion Mode.
TIMING SPECIFICATIONS
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
COMMENTS
tCONV
tACQ
tCKP
tCKL
tCKH
tF
tR
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Conversion Time
Acquisition Time
Clock Period
Clock LOW
Clock HIGH
DOUT Fall Time
DOUT Rise Time
CONVST HIGH
Address Setup Time
Address Hold Time
RD Setup Time
1.75
0.25
125
40
µs
µs
ns
ns
ns
ns
ns
ns
ns
When TCKP = 125ns
When TCKP = 125ns
5000
40
25
30
15
15
15
15
15
20
20
Address latched on falling edge of CLK cycle ‘2’
ns
ns
ns
ns
ns
ns
ns
Before falling edge of CLOCK
After falling edge of CLOCK
RD to CS Hold Time
CONVST LOW
RD LOW
CS to Data Valid
CLOCK to Data Valid Delay
Data Valid After CLOCK(1)
25
30
1
Maximum delay following rising edge of CLOCK
Time data is valid after second rising edge of CLOCK
NOTE: (1) ‘n – 1’ data will remain valid 1ns after rising edge of next CLOCK cycle.
CLOCK CYCLE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SERIAL DATA
CH0 OR CH1 CHA OR CHB DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
TABLE II. Serial Data Output Format.
ADS7861
SBAS110D
11
TI [ TEXAS INSTRUMENTS ]
